My project has been to design (and create) better EDA software that will simulate, optimize and therefore can form and place each individual transistor optimally to achieve lower power, higher speed and lower cost. There is only one drawback over all existing EDA software: my EDA tools must run on a ($100k) small supercomputer or FPGA cluster because it deals with a billionfold more transistors than existing EDA software and that takes more compute. It means my software is much cheaper than existing EDA software but will yield much better chips and wafers with much faster, better, cheaper and fewer transistors.
A high level overview of my software is mentioned indirectly in my talk https://vimeo.com/731037615
I'm eager to give a talk on my EDA software as well, please consider inviting me to give it?
Other researchers and companies have proven that optimizing transistor design and placement over standard cell libraries and PDKs can be done, for example:
https://www.micromagic.com/news/Ultra-Low-Power_PressRelease... was done with their own EDA software.
I am very certain (but have no hard proof) that this is what Apple did on their M1, M2, M3. M4 and M5 processors, especially their high end M2 and M5 Ultra chips.
What I'm claiming here is that humanity can design three to four orders of magnitude faster computer chips using at least two orders of magnitudes less energy making chips orders of magnitude cheaper if we only used better EDA software (CAD=> SYM=> FAB) that we use today. Moore's law is not at an end. I'd be happy to provide proof of this, but that takes a bit more effort than a HN comment.