Quick note - I’ve been where you are on hardware, which I imagine is “interested and curious and might have a use case”. Silicon is an industry that is
related to software, but in no way the same, and it’s a fairly complex stack, with its own unique supply chains and considerations.
All that said, if you’re exploring, have fun! If you’re getting serious I’d recommend you find someone who can help you navigate it; there are many surprising things to learn as you go.
For instance, to answer your question on chips: all chips are made by ‘taping out’ - a process that yields the masks that can be used to make chips. These are only good with a specific chip maker, and will live with that chip maker near the hardware that is used to make the chips forever. It’s expensive to design the chip, and expensive to tape out, but once you have something it’s relatively cheap to make more of them.
180nm is potato quality - many many generations behind. So far behind it might actually be more expensive to get chips than at 110/65nm, although I’m only speculating here.
A shuttle run means the vendor is going to put your chip designs onto a wafer with a bunch of other ones at the same time; it’s a way to share out the costs for a tape out with other customers. The general idea of a 180nm tape out is likely that you want some parts to test in your infrastructure / build ahead of your full launch. Think of it like a compile with -debug turned all the way up.
Usually you’d then either adjust the design and re-do a shuttle run (your compile turned up real problems or your use case changed), or you’d shrink and make your own wafer, (turn on optimization and compile for deployment). Shrinking from 180 to 110 or 65 is likely almost totally an automatic process these days; as you go smaller, analog physics makes this challenging.
So, upshot: you probably could ask for another shuttle run, but you’d have a higher part cost than your first run because you’d be paying for the whole wafer alone this time, but only able to use the part that has your chips on it.
And, you’d need to be in a world where you really wanted another 300 chips of the same potato speed (and possibly quality) as your first run. Most likely a silicon consultant would find a more efficient use case for your needs, whether that’s a small geometry FPGA that is programmable, an existing chip (there are A LOT of chips in the world), or some other solution.
Anyway, have fun if you get into it — fascinating world.