Syzygy: An open standard for low cost, compact and high-performance peripherals
syzygyfpga.io
syzygyfpga.io
i know it will probably never happen, but it would be 'truly epic' if hard PCIe endpoints became as ubiquitous as say, SPI peripheral blocks, within MCUs/MPUs and the general silicon jelly-bean world.
just a very high speed, very low latency, very widespread, very standard, very boring communication channel. and ofcourse an atmega328p can't keep up with the full b/w, but even something like an rp2040 could take serious advantage of such a fast port.
it would mean that fast information interchange would be available for "anyone", and most importantly, could be interfaced with a bog-standard run of the mill desktop PC.
it feels like, right now, if you want to do pcie stuff you have to either go FPGA, which seem like theyre quite far behind: artix stuff is pcie gen 2, i think gowin announced some pcie4 products but im not sure if they ever became real - and fpgas ofcourse are expensive and drag in a bunch of other considerations that you may not want or may be detrimental to your project... or go for a limited selection of (often closed source) mcus/mpus, thankfully the raspberry pi isnt that closed, but if the rpi doesnt have what you want then you have to go for say a rockchip, or whatever asian SOC that often has a very ambivalent relationship with datasheet availability. and even then they might not support operating the pcie in device mode (might be misremembering)
whatever, maybe im talking rubbish. i remember wanting to make some kind of USB3 gadget and being incredibly frustrated that the only option among the ocean of MCUs was the cypress ezkit bridged to a parallel bus to an FPGA. so lame! i think xilinx offered a usb3 peripheral IP block but it was behind an expensive license. i think since then there have become available USB3-capable RISC-V MCUs, thankfully, but im still surprised that nobody seems to really care about fast low latency data transfer. i guess its just not very important for "real" applications out in the wild.
As is, PCIe would add sizable die area consumption, raise power consumption by an order of magnitude, and likely raise part cost dramatically. Couple this with cheapy board designs that often can't even get USB 1.0-2.0 right (recalling the amount of boards that get the pull up resistors or power supply schema wrong), and it sounds like a nightmare to manage.
I think gigabit Ethernet is where I'd prefer the effort spent. Most micros have at most 100 Mb. NXP's i.MX RT line has gigabit but that's the only one I know of.
We are already drowning in transistors, I am not convinced by your area argument, esp in the face of shrinking nodes, we have more area than we know what to do with.
https://eps.ieee.org/images/files/TC_article_Universal_Chipl...
https://www.hpcwire.com/2022/05/11/intel-says-ucie-to-outpac...
I'd love to see UCIe scale down to SPI. I also agree on more pervasive use of Ge would be nice.
This gross look shows what I believe are some PCIe block die areas.
https://substackcdn.com/image/fetch/f_auto,q_auto:good,fl_pr...
This is roughly half the size of what I've seen to be some of the smallest micros, and those are most likely not on the same lithographies. When you combine the amount of additional RAM/ROM needed to run a PCIe stack, maybe divide by 4 for 1 lane instead of 4 to be generous, you're still likely going to double the die area used. On top of that which I didn't mention earlier is that PCIe transceivers are going to need more per supply circuity. ST's been doing a good job of integrating things in for stuff like DSI but those app notes show more complexity than the aforementioned atmega328p which is so simple it can sometimes be run without decoupling caps on a breadboard.
If you look at die shots for micros, a lot of the time you'll see most of the area is consumed by large arrays of SRAM or flash. And SRAM is known to not scale to lower lithographies. So, I don't expect to see this changing really. To be PCIe compliant you'll likely need to have the ability to store a full TLP. On a 328p, that could double if not more the SRAM needed. So the chip would get idk ballpark 3x bigger with all the stuff included? I just don't see manufacturers wanting to do this, which is likely why they haven't. There are very few cortex M chips with PCIe that come to mind. Some more cortex Rs. I figure if it was really the silver bullet, somebody would've done it by this point.
Please don't put words in my mouth.
I see what you are saying, but you have to put my whole comment together. I am not saying that 8 bit MCUs are going to get GB/s capable PCIe.
Look at things like https://www.efinixinc.com/products-titanium.html with PCIe Gen4 on a 40nm SMIC process. Or more apt, the https://www.wch-ic.com/products/CH384.html PCIe to printer port bridge.
Arguing that I think an Atmega328p should be running PCIe is a ridiculous straw man.
Also, Efinix hasn't proven themselves yet. I've been following their titanium line for years. Every year they say they're getting transceivers. And every part that comes out that was supposed to (first the Ti180, now the 375) is missing transceivers. Sidetracking here that I honestly don't know what's wrong with them, they've taped out a handful of these parts since I started using them, but they evidently cannot get high speed serial working.
I think we had some nifty ideas in there (using an analog voltage for peripheral addressing was one of my favorite). It has slowly seen more adoption as time passes. Would always love to see more adoption!
It was a pretty neat hack.
Placing small microcontrollers on the peripherals also opened up other functions like using them for basic power supply sequencing.
https://forums.sifive.com/t/friscy-new-high-performance-pcb-...
(Warning, hyperlinks are definitely gonna be broken from that post). I wonder how popular the interface has been over the last few years - I haven't really paid attention.
I am just aghast at how slow so much of the computing world moves. Cortex A53 is twelve years old, & still rampantly abundant & the go to option, or it's barely improved at all A55. We still see lots of A7's too for lower power, only barely beginning to be replaced by A32. The M7 has been a significant boost but the M3/4 are enduring. ADC/DAC have gotten a bit better for microcontrollers, but we are so far away from bandwidth & connectivity being competed on, being competitive.
This was a more hopeful future.
Things are moving very fast imo. MCUs can do 1080p at 30fps now and not just from faster hardware but with some impressive additions to instruction sets!
Edit: After re-reading I see that you're talking about adoption rates, in which case, fair points.
What's the point of low speed single ended I/O into an FPGA module? Seems like a waste of effort.
Hardware interfacing with the physical world. Driving small numbers of LEDs, h-bridge drivers, load switches, regulator control signals, reading buttons, accelerometers, gyroscopes, magnetometers, PWM controllers, GPS, ...
As for why to use single end low speed I/O, I guess it's about perspective. For some, an FPGA is something that sits on a PCIe bus or network. For a lot of people, it's a lot more than that. Something that talks to countless chips that maybe need spi, i2c, uart, or something custom.
For example, think about all those 1 wire LED strips and how it easy it would be to do that in HDL compared to the other approaches. Being and to work easily with bits vs bytes has huge advantages for custom interfaces. Another example: one time a group I was working with wanted to talk to battery management modules. Each one had a uart and they had to get daisy chained together, complicating things a lot. An FPGA with more than a few uarts is trivial and could've talked to each one independently. Even the highest end micros have maybe at most 20. You could fit 16 on 1 of these connectors. The UART block from Xilinx is on the order of 100 flops. You could have literally hundreds of uarts. Not that I have seen a need for that, but who knows, maybe someone does.
Getting rambley but another option is for test devices. Let's say you have a device that has a low speed interface and you want to test a lot of them at a time. You could use a bunch of multiplexors and time division control logic, or slap down an FPGA and do them all at once.
The lower speed Syzygy standard, while not operating at these speeds, is capable of much higher rates than a typical microcontroller. There are many peripherals with I/O requirements beyond a simple LED or SPI device, but below that of a PCIe or other high rate transceiver such has:
- moderate to high end ADCs and DACs (LVDS and parallel)
- image sensors (LVDS, parallel, and HiSPI)
- various networking PHYs
The lower end syzygy connector has pinouts to support LVDS differential pairs, which can easily achieve hundreds of Mbps data rates.