The usual speed bumps with these SMP designs show up in the white paper. There's a section on how they can use recompilation to automatically accelerate existing code. There's a rich history of failed attempts at automatic parallelization at compile time. So this section is just an admission that you're going to have to write code specifically for this thing to get anything out of it.
This coprocessor concept looks like it needs to be tightly coupled with the host CPU to work. The upside needs to be massive to justify a vendor integrating with this IP and also overcome the software adoption costs. Especially since they're directly competing with GPGPU...
Also some strange red flags, like the comparison to quantum computing in the FAQ. (Did they feel the need to include this because an investor asked?)
My guess is they've done some interesting core research around memory bottlenecks/latencies in a massively SMP architecture, and picked up investment to attempt to productize it. But the way they're marketing themselves right now doesn't inspire much confidence.