Intel Unveils Lunar Lake Architecture

It seems that they are moving from higher level (larger) building blocks to lower level (smaller) building blocks to increase efficiency.

I have a friend[0] that is doing his Electronics Engineering masters in Germany (very prestigious engineering university) and they're studying a freaking Pentium 4. Even for them the cutting edge chip design is black magic.

[0] Ultimate frisbee teammate.

So chip designs are spliced into partitions. Each partition is a part of your design that you synthesized separately. For example you may setup a partition for the core, and you can instantiate it multiple time into a core_cluster partition.

Note that: synthetiser's logical optimizer cannot work on logic across partitions, so you don't want to small partitions (otherwise you will have more manual optimize to do) but you also don't want too big partitions (otherwise runtime and development iteration time increase).

The question is what the good size for a partition ?

* ALU is ~ 10 K cells (synthesis runtime range from few seconds to ~5 min)

* small core (low-end) is ~1M cells (synthesis runtime range from 1~8 hours)

In the Intel terminology: "sea of FUBs" approach is to prefer small partitions, while "sea of cells" approach prefer big partitions.

About the predominance of latch or flop, it's mainly a consequence from the level of manual optimization. (latch are smaller, but harder to manage, and it give diminishing returns with new process node). Same for process-node-specific vs process-node-agnostic.

PS: Most modern designs are "sea of cells" according the Intel terminology

I may very much be wrong about it, but intuition and experience tells me that means of control usually empower authoritarian parties first and foremost, unless fully owned and operated by individuals - which, in computing, is very much counter the trend and the zeitgeist.

There are technical challenges in using secure enclaves correctly, and those limit adoption. At Anjuna (anjuna.io), we are working on those problems and seeing good results for our customers.

The world deserves competition in this space.

It's not looking good for Intel foundries.

I can't remember which WiFi generation I was testing this with but I remember seeing something like a 40% reduction, worst case.

The effect is well known, and the reason why if you open up your average phone, there will always be a ton of shielding around components. All the high speed buses can and do create lots of side emissions... so in order to allow a phone to function with its extremely tiny bunch of antennae in direct proximity to the chips, all components get shielded from each other.

In desktops and even most laptops however, the high-speed (and thus high-frequency) chips and their clock traces are very far away from the wifi/bt antennae, so for a long time manufacturers could get away with not shielding anything, just taking care about ground planes, trace length and impedance matching and spacing. Nowadays, with buses getting ever faster and faster (to the point where analog design criteria take over priority), I think we'll start seeing shielding rather sooner than later, and we're already seeing CAMM modules getting implemented in devices for the same purpose.

Side note: that's also why you're not supposed to operate a computer's parts without a case at all or with a partially open cases. The case itself acts like a faraday cage.

Nothing magic.

But the deep integration with better margins and higher end product prices allows Apple to have more expensive CPUs than the competition.

AMD and Intel can do what Apple does and Apple can do what AMD and Intel do, but each company chooses the path they believe it makes more sense for them.

Because the power consumption grows at least quadratically with the clock frequency, having the same speed at a lower clock frequency provides better energy efficiency.

Meanwhile, the difference in IPC (instructions per clock cycle) between Apple and the others has been reduced, but Apple still has a healthy advantage.

The different microarchitecture explains the energy efficiency advantage for single-threaded tasks.

On the other hand, for multi-threaded tasks, the power consumption per chip area is limited by cooling and the energy required to do a quantity of useful work (which is done by switching a certain number of logic gates) is mainly determined by the parameters of the CMOS process used to make the CPU die (assuming that the CPU designers are not incompetent).

So for multi-threaded tasks the better energy efficiency of the Apple CPUs has been determined mostly by the fact that they have been the only company able to use the latest and greatest TSMC CMOS process.

Apple have access to the newest and best fabbing processes from TSMC. That alone can put a chip a generation ahead in terms of efficiency. Intel foundries have been struggling for years and AMD only get TSMC's scraps a few years later.

Increasing clock speed is the easiest way to increase performance, but power increases quadratically with clock speed so it's very inefficient. Apple clock their processors pretty low and instead focused on increasing instructions-per-clock, which is generally more efficient but requires more die area. As an example, a lot of noise was made about the M1's 8-wide decoder, twice as wide as contemporary x86 chips, which is an important bottleneck for IPC.

Increasing instructions-per-clock requires much bigger CPU cores, and the dies Apple use for their SoCs are famously enormous. While other chip manufacturers are very conscious of performance/$, Apple's vertical integration gives them wider margins and their customers are much less sensitive to value. So Apple can afford to spend a lot more on bigger chips that are on par in performance but have much greater efficiency.

The other issue is that traditionally the integrated GPU has been quite anaemic.

32GB might not be enough for everything

In other words, even though it's on-package, the width of the memory interface is the same as previous generations. They also exclude upgradability unnecessarily, because even with on-package memory you can still support adding memory through slots. For example, the Xeons with on-package HBM allow this.

This decision by Intel seems specifically designed to screw the customer by forcing them to buy a new CPU (or computer) in order to upgrade the memory, without even providing the countervailing benefit that Apple gets from doing it that way. (Note that Apple too unnecessarily prevents adding memory at the traditional level of performance. Cache hierarchies are a thing, if you're not trying to screw the customer.)

??

WindowsNT shipped on x86, Alpha, and MIPS. Then got ported to X64, PowerPC and Itanium.

For the NT line, historically Microsoft was very supportive of other ISAs. The market wasn't.

(I worked on applications supporting a number of those. x86/x64 won the price/performance war).

Intel, AMD, Nvidia, Qualcomm + big tech giants like Apple are already producing them, MSFT is also planning to do that. I recall either Google or Facebook wanted too and so on.

Sure, plenty of windows users (business and personal computing) rely primarily on first-party apps, browsers, and big flagship apps (which could presumably leverage Microsoft partnerships to release on new architectures early enough that users wouldn’t notice much pain). But the long tail of widely used applications that aren’t big enough that I’d trust them to release ports by the time of an ARM (or whatever) hardware release is huge in Windows land—much larger than on MacOS.

They’re reportedly going for a 256 bit memory interface, and a way bigger GPU than what’s normal for integrated graphics.

Lunar Lake is specifically targeted towards power efficient laptops, there are no desktop chips, or desktop-class mobile chips. Its being positioned for Macbook Air competitors, a device which maxes out at 24GB RAM.

You get getter performance/watt but you can't upgrade. It depends on what you want.

You're out of luck.

The really big deal there is that this is an Intel processor built at TMSC.