Verilator: Open-Source SystemVerilog simulator and lint system

I have been bitten so many times by bugs in third-party IP that I almost never use it unless the company literally cannot build the thing that the IP provider is selling.

Many companies instead buy the IP and then spend almost as much time as they would have needed to recreate it having back-and-forth conversations with their vendor sending bug reports and reproduction test cases.

Verilator is amazing for building huge systems when you make that tradeoff. Yes, you will do a lot more RTL development for logic, but you have none of these vendor headaches and you get to write your testbenches in C++ and also run tests that are extremely long. A single computer can simulate an SoC design at reasonable speed.

The Antmicro team are doing good work with making Verilator support SystemVerilog / UVM tests but from what I understand it's not complete yet.

I've also heard from various people that although Verilator is generally fast, it tends to choke on compiling sufficiently large designs, whereas the Cadence and Synopsys offerings eventually get it done.

Still, Verilator is an awesome piece of software. Maybe the biggest thing recommending it: it's totally free, so the number of simulations you run in parallel is bounded by compute availability rather than licenses.

Shameless plug: I'm a cofounder of silogy.io, which offers hosted Verilator and other Verilog sims, plus debugging and collab tools.

Colleges and universities normally teach students the basics of digital logic and electronics before diving into Verilog or VHDL. At least that's how it was when I was a student many years ago.

You can learn computer architecture without knowing an HDL but it helps.

In my experience, commercial ASIC design in the US, VHDL is more popular in colleges and Verilog is more popular in industry.

Whichever one you like - they are basically equivalent in terms of what they can do. Verilog is more like C while VHDL is more like Ada.

We're in a golden age of youtube videos teaching you the basics of Verilog/VHDL, digital design, computer architecture, FPGAs, CPU implementation, etc. Starting in simulation (like verilator and gtkwave) is a great idea because 1) it's free 2) you get easy visibility into the low-level behavior of your design and 3) simulation is an important part of hardware design, testing, and debugging.

Besides HDLs (which are great) you can also use block design tools; for example, hneemann's Digital (which was influenced/inspired by Logisim) looks like it could be a nice learning, development, and simulation tool - and it also exports to Verilog and VHDL. There are several web-based environments as well.

I've also recently run into some other HDLs which look interesting, such as Migen, which is used in the LiteX SoC framework and implements an HDL as a Python library. (It also has successors which I have not used.)

And on a semi-related note, Patterson and Hennessy's "Computer Organization and Design (RISC-V Edition)" is an updated classic introduction to computer architecture (and its sequel is legendary.) I also recently discovered Harris and Harris' Digital Design and Computer Architecture (RISC-V Edition), and its follow-on lab courses, RVfpga and RVSoC, which cover implementation on an FPGA board and/or simulator.