Memory Consistency Models: A Tutorial | Hacker News Reader

Memory Consistency Models: A Tutorial

cs.utexas.edu

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> A barrier instruction forces all memory operations before it to complete before any memory operation after it can begin. That is, a barrier instruction effectively reinstates sequential consistency at a particular point in program execution.

> Of course, this is exactly the behavior we were trying to avoid by introducing store buffers and other optimizations. Barriers are an escape hatch to be used sparingly: they can cost hundreds of cycles.

I may be wrong, but I think to readers who do not already know what barriers do and are, this makes barriers seem like blocking behaviours.

Just to clarify your comment via a question: are you pointing out that barrier instructions are a scheduling ‘issue’ that the processor uses to order instructions versus something like a memory read that actually requires a pause in the execution of instructions?

Mmm. Sort of the former, but really my thought was this : "you have a barrier, fine, but that does not mean once you hit/pass the barrier, all prior read/writes are complete - in fact, the completion of earlier reads/writes only occurs at the first read/write after the barrier".

Barriers can induce blocking behavior though. A store barrier followed by a store operation can result in a blocking operation until the store buffer is flushed, and similarly for a load barrier.

The usual way that barriers were implemented was to simply stall the CPU pipeline. So yes, they do indeed have blocking semantics. IIRC mfence still does stall the pipeline on x86, but I think the CPU is a bit smarter for locked instructions.

I'm about to move into ARM development for a new-ish AI accelerator. Until now, I've mostly developed for x86.

In preparation for this, I've been reading up on ARM's looser memory consistency model, and C++'s rules regarding this. It's been pretty eye-opening.

I'm looking forward to seeing how much that ARM codebase takes advantage of the weaker guarantees that ARM permits. It seems like a trade-off of scalability vs. correct-code complexity.

It's mentioned briefly at the end of the article but this book from Morgan & Claypool is great: http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2...

what is the "dense tome" that the author refers to in this link: http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2... ?

it seems to be coming up kinda 404 for me. thank you !

Probably "A Primer on Memory Consistency and Cache Coherence"

Hi, would you recommend this book in 2024?

FWIW, most of my recent knowledge on this topic comes from [0].

The programming-language-specific parts are more focused on C than C++ (which is my main focus), but I've still found it quite helpful.

I haven't looked at the other sources people are mentioning though, so no idea how it compares.

[0] https://cdn.kernel.org/pub/linux/kernel/people/paulmck/perfb...

Thank you, I will give your resource a read :)

You're welcome! But it's not a quick read.

At least for me, it requires (a) a good reason for powering through it, (b) a good night's sleep, and (c) Adderall :)

Just saying, it may not be the most effective / efficient way to learn what you want to know.

Ahaha, luckily /s I am a bit of a weirdo and I like to delve deeper into things related to my job.

I was taught that a deeper understanding leads to better software/solutions and I strive to live up to my mentor dedication :)

> I was taught that a deeper understanding leads to better software/solutions

aside from being fun, it just makes everything so much easier when it's not "magic"

Yes

See also https://www.cs.cmu.edu/afs/cs/academic/class/15740-f18/www/p... and Gharachorloo's thesis paper.

@sdbbp, thank you kindly for the references, both are excellent !

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