I think you are a little optimistic that the full EDA flow would be "not... particularly difficult to write." On the implementation side alone, you'd need to write a SystemVerilog compiler, logic synthesis, timing analysis, timing optimization, power analysis, clock gating, coarse placement, global routing, detailed routing, placement legalization, physical design planning, clock tree synthesis, design rule checking, lots more underlying technology to make it work, and lots of steps I'm not remembering. Every one of those sub-areas is it's own specialty. Then you can start thinking about verification.