I'm not an expert on memory interfaces. How do you use HBM2's 1024-bit interface when you have ~200 I/O on a zynq ultrascale+? Are these psuedo-channels a SerDes for the HBM2 bus?
You end up with a similar challenge accessing that much bandwidth internally from your FPGA logic though, it looks like the Xilinx HBM IP presents a set of 16 or 32 separate AXI interfaces, each of which gives you about 14.4GB/s of bandwidth (https://docs.amd.com/r/en-US/pg276-axi-hbm/Introduction).