Would it be at all feasible to build a physical NAND-to-tetris computer? Or is it purely a virtual exercise?
But you can Google "nand2tetris fpga" for more.
EDIT: there's more information here: https://www.megaprocessor.com/
It's been a few years since I studied it (I even built the clock module, registers and the ALU), but from what I remember the biggest departing point from what you want is that the control logic (from instruction decoding to deciding which sub-units to activate for each instruction) is done with an EEPROM instead of individual logic gates, as described here: https://eater.net/8bit/control
61 TTL chips mentioned in this 8 minute overview https://youtu.be/3zGTsi4AYLw
It displayed on a VGA monitor.