1800-2023 – IEEE Standard for SystemVerilog | Hacker News Reader

1800-2023 – IEEE Standard for SystemVerilog

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53 pointsfargle18 comments

Nice. Shame the VHDL standard isn't yet free to get. Given it's mostly Ada, for which the spec is freely available, I'd have thought VHDL would have been available before Verilog. Oh well.

Open source VHDL is in fairly good shape with GHDL and NVC. I sometimes visit https://app.gitter.im/#/room/#vhdl_General:gitter.im and I sometimes see the developers of those projects providing really great feedback, sometimes by answering questions from VHDL standards group members.

For the best VHDL and Verilog ecosystems, the standards should be freely available. It's madness when the standards are not available.

The 2023 version of the System Verilog standard has been released.

It's free via the IEEE "Get" program, which is awesome.

Why can we not have a simple pdf download button?

I’m surprised it’s available at all and kudos to them for making it so.

I’m sure the folks who worked on this are hard working and dedicated and all of that, but the entire IEEE standards process seems like a backward, political, and entirely pay to play model.

Based on my experience, they won’t even talk to you unless your company joins their consortiums and whatnot. And why would they? Their members benefit directly from the “moat” of complexity they have created. As an outsider, you may as well not even bother trying to report errors, etc.

These standards are fortunately an actual easy download elsewhere.

It is really irritating that what should be the authority on these documents does require going through hoops. Particularly as we're talking standards, which should be implemented as widely as possible.

I read 1800-2023 and thought wow, System Verilog had a great run, shame it's over.

the differences from 2017 are relatively minor, so apparently that's not recent news? nobody told us tho. /s

I think you may have misread the parent comment in the opposite way that comment misread the title. Isn't it a bit sad that System Verilog ended after a bit over two centuries?

The LRM is probably the best thing about SystemVerilog. Does a fantastic job of being a reference and an actually readable document you can learn from (which is lucky because the other SV resources on the internet are very sparse).

Just a shame about the language itself.

Nice! But OMG, the LRM has really grown from the Verilog 1995 days - 1354 pages! Though very readable.

LRM = Language Reference Manual ??

Correct

Any summary of the biggest/most impactful changes?

quick summary: not a huge change

one that is interesting is that they've improved `ifdef to allow boolean combinations. it was previously hard to accomplish what CPP can do with #if.

i wish there were change bars, but could not find a draft or a way to do a meaningful diff.

there's a paper by Dave Rich: https://dvcon-proceedings.org/wp-content/uploads/1114-Whats-...

Preprocessors make language parsers cry.

it would make me very happy if someday someone does a really comprehensive study of the places where specific techniques cannot be accomplished without a C/C++ style pre-processor. SV is very similar to C, but actually even less powerful. step #2, find a way to build a better macro/meta-coding system within the syntax of the language to eliminate the need for a textual pre-processor.

in SV, generate constructs are exactly this concept and have reduced the need for macros significantly, but we still can't quite get rid of them. but at least for me they are pretty rare.

I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be <the language> and also have a textual preprocessor defined internally. It doesn't work.

I really like what Zig and C++ are doing with `const`.

https://ikrima.dev/dev-notes/zig/zig-metaprogramming/

Have you looked at Spinal?

https://github.com/SpinalHDL/SpinalHDL

https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html

edit, I see in your post history that your first submission was on Prosser's macro expansion. https://www.spinellis.gr/blog/20060626/cpp.algo.pdf :)

zig: yes, it's very interesting. there's other parts i'm not sold about, but that idea is very interesting.

spinalHDL: yes, also interesting. although honestly, i really prefer SV. it's a shame that the language has become so complex, but a synthesizable subset still ends up being the best thing for me to efficiently describe hardware. what they did with generate() and parameterization (borrowed from VHDL?) is very nice. it's far, far, better than C++ templates for an analogous purposes. i very rarely need to use `if, `define in SV nowadays.

cpp: oh yes, i'm a nerd about languages/macros/meta-programming/etc.

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