Control Data Corporation's CDC 6600
chipsandcheese.com
chipsandcheese.com
There famously were not interrupts in the classical sense in the 6x00, but PP's could read and scribble anywhere in central memory, and they could compute an address and jam it into the CPU's PC. So in effect infinitely flexible vectored interrupts.
4Kx12 is not a lot of program space, so most I/O drivers consisted of one or more PP overlays that would be loaded depending on which I/O device was in use.
If I recall correctly, the operator console required a PP full time -- the console being a couple of CRT's with shared X & Y DACs, and independent Z DACs, so they used vector fonts for everything. A second PP was full time dedicated to scheduling the other 8, at least in the common operating systems. (There were a bunch of operating systems... but I won't get into that.)
Also... somebody (maybe Seymour himself?) worked out a 12 word boot loader... and PP0 had a switch panel of 144 toggle switches arranged in a 12x12 matrix. You could toggle in the bootloader once, and leave it forever. At boot time those 12 words were loaded into PP0 core.
The peripheral processors were indeed a 10-way SMT thing, which they called a barrel processor. Each thread had three registers but they operated in really strange ways, and I just didn't figure that out.
There were other details like bandwidth being tied to bank count, which I also didn't go into.
> I suppose the picture of computing is of a topsy-turvy growth obeying laws of a commercial "natural" selection. This could be entirely accurate considering how fast it has grown. Things started out in a scholarly vein, but the rush of commerce hasn't allowed much time to think where we're going. — JET
I was amazed to read some of what he wrote at the time about the 6600 design and consider how qualitatively modern it sounds (if one is willing to add zeros and change units where quantitatively needed).
The other extreme was the Pentium Pro, the first superscalar x86 CPU. I went to the talk at Stanford where the lead designer described the architecture. That was the most insanely complicated CPU built up to that time. People were thinking RISC was the future, because nobody could possibly get something as messy as x86 to go much faster by architectural means. But Intel brought it off.
One of the speaker's graphs showed the number of engineers involved over time. That peaked around 3000 people. Just getting that many people to work together to design one tightly-coordinated thing was an impressive achievement.
The number directly from the Pentium team was 3000.0000000001 people at the highest point.
Pretty bold claim, can you explain why you believe this is so?
> But Intel brought it off.
Not by buying up and killing the Alpha AXP, oh no.
Intel had little to do with it.
We'd be living in a different world if they'd put all the money from the VAX 9000 into RISC CPUs instead.
There's reason why so many places kept to Digital gear even after Compaq mishandling, then the Itanium and HP days, and not all of those were customers that had problematic rewrites blocking any migration (like customers dependant on VMS).
Yes, Windows NT Alpha did take off initially and was the go-to non-Intel platform for CPU hungry apps, but it was expensive and then Intel caught up with multi-processor Pentium Pro systems and that was the end of the Alpha.
Sun SPARC/UltraSPARC was effectively a hardware appliance to run the Oracle database (and SAP). SGI/MIPS covered the 3D graphics market. IBM POWER was the hardware to run DB2 and other IBM wares ported from mainframes for customers who did not want to have to deal with JCL and other hairy stuff. HP PA-RISC was an enigma that ran something although not that many people were sure what exactly it was. HP Superdome was pretty rad tho – I worked on a project for a telco that had purchased a 128 CPU Superdome to run their billing system on (ironically, it was IBM who had sold them on the Superdome). HP-UX before v11.21 had been buggy AF and overall an abomination.
Yes, Alpha could run Oracle as well, plus other things… they never seem to have taken off tho, and Alpha was quickly relegated to an IP garage sale.
From the technology perspective, Alpha was a resounding success, at least in the beginning.
From my perspective, Alpha had quite wide user base, not as much as Sun which seemed to have figured desktop unix sales way better than everyone else. I know some segments tended to buy Digital because if you knew what you wanted, Digital would let you simply order it - disappearance of that approach, forcing everyone to go through a sales rep, has been anecdotally pointed to me as why a bunch of places migrated post Compaq acquisition.
It was a general purpose processor, talking about a single killer app doesn't make sense. It was designed for speed and expandability and as such seemed very successful.
The Pentium Pro was Intel's first out-of-order design. It's also superscalar.
StackOverflow has a really funny post by Andy Glew, who worked on the Pentium Pro, noting that a scalar out-of-order machine could make sense in some corner cases. (https://stackoverflow.com/questions/10074831/what-is-general...)
The thing that Seymour had going for him at CDC is that he didn't bother with synchronous exceptions. On x86 (I worked on a late 486, Pentium I, Pentium II and Itanium II) you absolutely must have synchronous exceptions for backward compatibility. Debugging an exception on 6600 was a hair-tearing exercise, because the PC point somewhere near, not at, the instruction that raised, and there may be a swiss-cheese window of instructions that did not complete somewhere before that. Loads of fun for one and all. (I used 6600/7600's while working on Cyber 203/205 at CDC).
You'd go down this "hall", the walls full of millions of wires, carefully looped so that the signals wouldn't arrive too early (1 foot = 1 nanosecond, and you wanted all the signals of the bus to arrive at the same time, which meant the all the wires on the bus had to be the same length.) "There's the address bus, now down the hall there are two rooms, one is the ALU, the other is the optional square root calculating units....
Yeah, a whole "room" to calculate square roots. I guess they hadn't figured out the fast square root algorithm which DOOM used yet :-)
Absolutely astounding artifact. It was like seeing the great pyramids.
ah the days of yore
If you use a different definition of superscalar (just having concurrent operations in flight), then I guess that applies to the CDC 6600? Then it'd also apply to any pipelined core, including stuff like the Intel 486.
For instance, if Ax is the base address, and Bx is the stride, you could do A4 = A4 + B4 ; loading X4 by side-effect A3 = A3 + B3 ; loading X3 by side-effect X1 = X5 + X6 ; do an add of data loaded in the previous unroll of the loop A2 = A2 + B2 ; store X2 by side-effect, presumably computed in previous unroll
All 4 of those fit in one 60 bit word. And if you are clever with loop unrolling and instruction timing, you can get a lot of overlap.
The 6600 had dirt-simple opcodes that took about a week to memorize, but.... that was a long time ago, so sorry I can no longer assemble machine code in my head. Memory fading.....
One can dream...