LLVM/GCC target fixed ISA devices. Even GPUs can be represented in this paradigm of having a core set of instructions and registers for SIMD/SMT. What FPGA or random ASIC could LLVM front-end? How do you go from LLVM-IR to something that can live in an FPGA?

You can either do what most "high-level" or "new HDL" tools do which is emit some form of "RTL" (Verilog/VHDL) or you can stick a place-holder design in the FPGA and then your LLVM-IR is basically emitting instructions for an "overlay" type of design.

And if we are being pedantic you can use Verilog or VHDL to write a purely STRUCTURAL netlist which includes hard instantiating "basic building block" primatives. i.e. have your RTL instantiate an ISERDES or OSERDES block (which I suspect will mean something to you).

But even with a "netlist" based design in RTL you still have to technology map that into building blocks of your hardware and that whole process becomes so complex people have just migrated to writing "behavorial" RTL (or translating to it from some other language, i.e. Vivado HLS).

Lastly, Vivado does support EDIF netlists as do most FPGA tools (whether they advertise it or not) but if you don't have a way to do a technology mapping stage from your high-level RTL into building blocks (which is effectively part of the "synthesis" steps), then what did you accomplish?