One can get quite small even with DUV (193nm ArF) by using high NA (water immersion) to get 1.3-1.4x better resolution (wavelength scales with index of refraction). That along with multi-patterning (which puts limits on the design layout, but allows 2-4x tighter pitch) can get you down to a pitch of about 65nm (single patterned) or 10-20nm (multi-patterned). However, the whole idea of pitch for the gate length falls apart around here and 40 is basically the same pitch as 65 with transistor packing tweaks, and 28 is the last "analog" node. By the time you're multi-patterned bellow 22nm, you're using fin-FETs and the scaling is totally broken (some would say made-up by marketing). That's how TSMC's 7nm was the same pitch as Intel's 10nm. Quad multi-patterning's poor yield finally broke the long dominance of 193nm, but it was cheaper than X-rays for about 20 years (and a lot of bankruptcies).
The use of the name EUV with 13nm wavelength and now immersion EUV, which allows 2-3nm without multi-patterning is meant to evoke the extension of lithographic techniques rather than the revolution X-rays implied 20 years earlier. Note that it's still so expensive that only a few critical layers are patterned with EUV. Double patterning will double the costs (half as many layers patterned per stepper per hour) so all the old tricks will come out again. Transistors will evolve again with nano-sheets and GAA to reduce leakage at even closer spacings. We should get below "2nm", but you're not talking about gate or metal dimensions anymore, just peak transistor density is ~400x better than 40nm (1M/mm2 vs 400M/mm2).
When you're selling $100M pieces of equipment in a field wit decades of history, names matter.