Nope. Quote:

https://en.wikipedia.org/wiki/7_nm_process

> The phrase "7 nm" does not refer to any dimension on the integrated circuits, and has no relation to gate length, metal pitch, or gate pitch; since at least 1997, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to physical properties. However, the smallest dimension within an individual transistor, the fin width, can sometimes be 7 nm. TSMC and Samsung's "10 nm" (10 LPE) processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density.

It's a standardised "process" sizing established by the International Technology Roadmap for Semiconductors. Originally they did correspond to actual feature sizes but since around 1997, they no longer correlate to actual sizes and are more just a marketing term that matches the same naming scheme as previously.

Occassionally a given process will correspond to actual sizes but it's more out of luck than anything else.

1nm is the real physical size of a transistor that you would need, to get equivalent performance characteristics, if the transistor's other layout characteristics were fixed in 1997.

The divergence is because when FinFET layout was introduced, it gave as much of as improvement as a node shrink would have otherwise done.

See also: AMD Athlon "3000" CPUs, clocked at only 2.x GHz, performing "as well as an equivalent" 3.0GHz Intel CPU,

The hype-to-reality gap is going to keep getting much bigger every generation of announcements due to Dennard scaling and the end of Moore's Law. I was fortunate enough to be an active computer technologist through the "golden age" from 1980 to ~2010. Every three to four years things got about twice as fast for around half the cost. And not just some features or aspects but almost the entire system in almost every way. We had no idea back then just how extraordinary that period was.

Today, the industry has regressed to hyping tiny incremental gains in narrow sub-metrics which only rarely have a material impact on overall performance across an entire system or most applications and usually at higher cost. Those that entered the industry in the last 15 years don't really appreciate just how much progress has slowed to a crawl.

Sadly, looking at the ten year roadmap projections from the likes of IMEC, there aren't any big leaps on the horizon. Progress will come mostly in single-digit percentages and most gains will be increasingly conditional (eg limited to one logic type or only in certain contexts). And the costs are going to keep skyrocketing. I hope we'll "get lucky" with some unexpected breakthrough but there's no reason to expect that.

It's true that marketing sort of ran away with it but it's important to note that the original idea was sound and didn't have to do with marketing hype. "Process shrinks" require many different industries to coordinate or else nothing can get done, and the ITRS roadmap was meant to be the mechanism to accomplish that coordination. What happened was that not long after it was introduced the actual feature sizes diverged from the names on the roadmap, but they decided to just keep using the roadmap names because the need for coordination didn't actually go away and, well, the names were right there, why bother changing them.

The end result seems crazy now but it's the result a set of decisions that were individually rational, not marketing-driven, at each step.

These gate and metal pitch numbers don’t tell the whole story. In the end it’s logic gate density that counts.

And while decreasing the gate and metal pitch, also the logic gates have shrunk to be smaller (typically expressed by measuring the height of a gate in amount of metal tracks) from 9tracks down to 6tracks.

Changing the transistor from planar to fins, and now hopefully to ribbons with eventually stacked pmos and nmos are a big enabler.

That said, we’re still not hitting the ideal scaling numbers. We’re just doing somewhat better than what’s suggested by poly and metal pitch only.

Well nm is not something anyone should care about. Chip designers care about gate density. But end users only care about speed, power consumption, capacity, etc.