Calyx: Intermediate Language for Hardware Accelerators
github.com
github.com
I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.
That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."
A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.
There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].
rachitnigam, do you have any example designs of "significant" complexity? I looked over the paper and saw your 2x2 array example -- I'm curious if you make this something like 100x100 or n x m, can that be done in parameterizable way? What about control-structures like bits to enable / disable functionality, etc?
Also, do you provide a way to do things like arbitrary insert pipeline registers and let your tools track that?
One comment when comparing to Vivado HLS, fundamentally HLS breaks all problems down into CSP-style designs (whether you want that or not) and it takes a lot of experimentation with #pragmas to get a more optimal design. Not claiming Vivado HLS will beat your tool, but it's possible with some tuning to get a "better" design.
HLS-like languages are an input to Calyx. For example, we're currently building a Vivado alternative using Calyx and the frontend there does the pipelining for us. Calyx then goes in and performs a bunch of other optimizations.
A big edge we have is that Calyx supports both statically-scheduled circuits (where the latencies of things are known) and dynamically-scheduled circuits (where latency is not known). Because of this, we have been able to do optimizations in this new flow that take advantage of both.
It's easy for people to do a lot of naysaying, it's a lot harder to try and actually do something evolutionary, let alone revolutionary. Please keep posting with up-to-date results.
Or is that left to you to build a driver separately for?
ASICs require a lot more work by either packaging on the same chip as a processor or building IO interfaces for their own package.
The premise of Calyx is you're generating hardware designs from high-level code which has a lot more structure than arbitrary HDL code and the compiler will use that extra structure to automatically do optimizations that cannot be done over arbitrary HDL code.
What platform/browser has this problem?
But http://www.bbc.co.uk works.
http://rachit.pl/files/pubs/calyx.pdf fails. I suspect /PDF/.
So we should have just stuck with schematic capture, then? Why were HDLs and logic synthesis developed (by those pesky "clueless" software engineers)? To increase productivity. Current HLS can (especially in certain domains like DSP) increase productivity. Sure, I'll agree that some of the hardware oriented DSLs probably weren't all that necessary if you consider the existence of things like generate statements in VHDL and SystemVerilog. But that doesn't mean that experimentation in increasing abstraction (and thus productivity) shouldn't take place. If yours was the reigning opinion in the software world we'd still all be programming in assembler.
2.2 Optimizing Accelerator Designs High-level specifications of accelerators encode a treasure trove of control flow information that is lost when lowering to a registertransfer level (RTL) language.
"Developing Hardware is a solved problem"
For which audience specifically? Maybe if you consider giant teams at large corps pouring in millions. Is it a solved problem for hobbyists, students, people who're just curious? Most people who're curious about software can go play with it in 15 mins. For hardware, it's more like months.
"If you need pseudo-DSL ..."
Weirdly gatekeepy. Why should hardware be only used by experts? There's lot you could've said about it being hard to optimize hardware well (which is challenging with HDLs too) but instead choose this argument.
"You cannot abstract away this engineering task" The goal of research is to try to do things differently. We already know how to build hardware using HDLs, with waterfall models and giant teams. We want to figure out if there are better ways to do it.
The VLSI revolution wouldn't have happened if randos on the internet kept complaining about how "we already know how to do full custom design" and "you cannot abstract physics". We did before, and it changed the world. Let's have some optimism.
I think, failure is a way better outcome than not trying in the first place.
The Google VCU paper explicitly mentions using such tools made them faster. All of these is enabled by people looking at problems with a fresh perspective
Maybe another perspective is that "outsiders" may not have the same view of the issue as experts in the field and may not (historically, in OP's experience) seem to want to work together with the experts to develop this view. Handwaving away complexities and not willing to get hands dirty is something I've seen as well so maybe I'm a bit more empathetic, but cold shoulders from "experts" towards newcomers is definitely a thing.
Both of which could help both sides - bring more depth to the fresh view of the "outsiders" and actually bring valuable freshness to the depth of the "experts".
> misplaced attention from outsiders and science/research community.
Come join the software side and work on the tools you want to see.