https://www.tomshardware.com/news/intel-demos-meteor-lake-cp...
For this same reason (timing precision) you see that soldered DDR5 memory often reaches way higher speeds than what's available in DIMM or SODIMM form.
I wonder how they will do this in the workstation and server space, I don't really see how they can do away with socketed CPUs.
I wonder if we will go back to slotted CPUs, with a SOM style board with CPU and memory being plugged into a motherboard/chassis that's really just an I/O back plane. How will multi Cpu communication look then?
I guess we already have memory being pinned to a NUMA node and connecting to others via a vendor specific interconnect, so maybe it's not that strange and different from today.
I'm guessing the endgame will be consumer parts all being RAM-on-package with no external memory interface, and workstation/server parts will take a hybrid approach like Intel is already doing with the Xeon Max chips which have 64GB HBM on the package and an external DDR5 interface supporting terabytes of slower bulk memory.
Sockets still make sense because you can choose between 10 or so different CPUs for a particular socket format.
But with just in time manufacturing you can imagine ordering the CPU directly from the motherboard manufacturer which solders it in place.
Given that AMD has been releasing AM4 CPUs since 2016, I think it's reasonable to assume that many of those who know how to build computers in the first place have upgraded their CPU. Why switch the whole motherboard/CPU combination when you can just plug in a better CPU?
Or would the cost of the extra complexity of the memory controller likely not be worth it ever?
[1]: https://www.anandtech.com/show/13560/amd-unveils-chiplet-des...
[2]: https://www.intel.com/content/www/us/en/gaming/resources/how...
the reason to separate all the components are to ensure high percentage of functional pieces
Intel's already doing that with Xeon Max, it has both onboard HBM and an outboard DDR5 interface. It can be configured to run entirely from HBM with no DDR5 installed at all, or use the HBM as a huge cache in front of the DDR5, or to map the HBM and DDR5 into different memory regions to let software decide how to use each. I don't think there's been any indication of that approach filtering down to consumer architectures though, Intel is talking about doing RAM-on-package there but without any outboard memory interface alongside it.
Most software isn't even NUMA aware, and would completely fail to take advantage of a tiered memory hierarchy if it was given the option. But if we make the fast memory a big cache and let the CPU worry about it it's a "cheap" win.
Though there is the Xeon Phi which has about 16GB of on-package memory that can either be configured as cache or as "scratchpad" memory. But of course that's not meant for general-purpose software
AMD 7950X3D, a desktop CPU, has 144 MB of L2+L3 cache memory on-chip.
I would say it’s even more strategic than the original.
ARM Holdings;
Imagination Technologies (UK) - PowerVR GPUs (mobile, automotive, embedded)
NXP Semiconductors (Netherlands) - GPUs for automotive & industrial
STMicroelectronics (France/Italy) - GPUs for automotive, industrial & consumer
BrainChip (Australia, subsidiary in France) - neuromorphic computing chips (similar to GPUs)
Graphcore (UK) - intelligence processing units (IPUs) for machine learning (alternative to GPUs for some applications)
InCore Semiconductor (Netherlands) - custom high-performance computing (HPC) solutions, including GPUs
Kalray (France) - programmable processors for data centers (alternative to GPUs for some applications)
RISC-V International (non-profit, enables European companies to design own GPUs)
Think Silicon (Greece)
...any others?