As your workload grows in thread count, processors become limited by memory bandwidth per socket, as well as power and thermal constraints. The 'big' cores can only perform at their peak frequency, power draw and IPC when not in a high multicore workload. So you end up wasting silicon resources, power in an all-big core design. Instead if you make the last several cores to be turned on smaller and optimized for a lower power state, you can fit more of them in, and achieve higher overall thread throughput for a given die size or power/thermal envelope.
So imagine you set a given budget for silicon die size and chip power. You might then have 3 design possibilities. Say 8 big cores, 16 little or 12 in hybrid. The hybrid design should be able to match the all-big in single/lightly threaded loads, while beating the all-big in highly multithreaded. These tradeoffs of course work best in form-factors that are constrained by cost or battery power. Which is where you see amd using them in consumer. Or by space/power where you see AMD giving choice of small/dense core options in Epyc.