The interesting part of the article isn't the processor but rather the LPDDR5 memory, which apparently has ECC support. I'm not aware of any vendors offering such memory - does anyone know which exact memory they're using?
[1]: https://forum.level1techs.com/t/ecc-capable-verified-motherb...
Your link is only about the current ASRock desktop MBs, not about AM5 MBs in general, not even about ASRock AM5 MBs in general. Previously all ASRock desktop motherboards supported ECC, but their current generation of desktop AM5 motherboards no longer supports ECC.
On the other hand, ASRock Rack makes some full-featured server boards with the AM5 socket and ECC support for desktop Ryzen 7000 CPUs, which have a much better performance per dollar than any alternative with CPUs that are sold as "server" CPUs.
For normal desktops or workstations, ASUS remains the most accessible choice for motherboards that support ECC. They also have many motherboards that do not support ECC, so the MB specifications must be checked before buying (a good ECC ASUS MB is PRIME X670E-PRO WiFi).
While the hardware ECC of Ryzens appears to be OK, their software support is much worse than that of Intel, as unfortunately it is usual for AMD.
Their Linux EDAC driver for Ryzen CPUs had not been updated for many years, since the Bulldozer times until about a year ago. A couple of years ago, many features, like testing without having to overclock the memory, by injecting errors, no longer worked, due to mismatch with the hardware.
During the last year, the AMD EDAC driver for Ryzen CPUs has been updated multiple times, so perhaps now all its functions work fine, but I have not verified this.
In-band ECC is a horrible workaround, which has a real hardware cost much higher than traditional ECC, in additional die area, increased energy consumption and much lower performance.
Intel has published some information about their in-band ECC controller, while NVIDIA, as usual, is much more secretive.
The performance of in-band ECC would be unacceptable without the addition of a special rather big cache memory and a great increase in complexity in the memory controller, which is required to implement clever caching algorithms. No matter how clever is the caching algorithm, there will still be workloads where the performance will be much lower than with standard ECC.
You lose data space for syndrome bits. This is not, in practice, different from fixing data space and adding chips for syndrome bits, but it reflects differently in specs.