The 100MHz 6502 (2022)

Yep. The 65C02 has a SYNC output that goes high to indicate an instruction is being fetched on the current cycle. Since there is no cache, it's pretty simple to use this to determine the PC.

You bank switch then. A common use would be to e.g. be able to use the ROM to load code into the RAM under the ROM and then bank switch, but also e.g. for extensions where you might want to first copy the ROM into the underlying ROM, and then patch whatever changes you wanted into before bank switching.

The thing you describe about replacing PC with an LFSR has actually been done, to simplify the silicon. Some very cheap 4-bit micro controllers, often used for TV Remotes, in fact, do this.

I think of this too. And I break it down into ads and operations. An ad is simply summing two inputs of some kind. In operation, might be a change of state or an input coming online or going away. Something analogous to the bit operations and or not exclusive or and friends.

With all the physics talk of information being fundamental, I suspect we will find both an upper bound and a lower bound.

The upper bound will be something like compute power per volume divided by energy or some similar construct. Basically you can only pack so much information and so many operations into a given region of space and energy level possible for that energy for that region of space to contain.

The lower bound might be something like the plank constant for computation. What's the smallest unit of space and energy level that can support an add, for example. It's interesting to think about.

Sorry for the typos I used voice dictation on this one

... and adding an integer to a pointer would be hellaciously expensive.

If you have the foundry SPICE models you can calculate these kinds of lower-limit values. I did this for 45nm a long time ago and vaguely recall getting numbers down in the double-digit femtojoule range for 32-bit addition, measuring only transistor R+C.

But the transistors don't really cost anything; all the CV^2 is in charging and discharging the wires. And the "C" is totally geometry-dependent. It's not like software -- at least not when you're pushing all the limits -- everything affects everything else.

>I wonder what the limit of computing power per joule is

Today you're going to learn that the universe puts a hard limit on this known as "Launder's principle".

To derive it in short, the (information) entropy on the input side of a single traditional logic gate is 2 bits, but on the output side it is just 1 bit. This seems to imply that the (physical) entropy of the computer would go down after the computation, because your computer had more possible physical states it could be in at the time of input than it seems to have at the time of output. But this is impossible as it violates the 2nd law of thermodynamics.

To resolve the contradiction, each logic gate must be putting the missing bit of entropy on an untracked non-computational degree of freedom within the physical system. In other words the untracked "missing" information is encoded as seemingly random waste heat, and dumped into the environment at room temperature.

https://en.wikipedia.org/wiki/Landauer%27s_principle

You are wrong, as polling always introduces jitter (due indeterminacy of the event arriving moment between the last entry to the polling loop and the comparison operation). If you want really precise timing while reacting to external event is to sit in "halt" state, with interesting interrupts enabled.

Another micro = big BOM cost increase

Another core = overall device cost likely unnecessary.

Both blow the power budget up.

Regarding determinism, relative to what?

An interrupt will, or can be very consistent relative to the signal. Polling jitters relative to the same signal. That may not be desirable.

Now, I did see you mention a Propeller chip!

The first chip worked as you describe and it is beautiful.

There are good reasons why interrupts were added to the second generation chip. They are mostly the reasons found in this discussion.

I was a part of the P2 development. We had a TON of discussion on this topic. Fascinating. Let me share an observation:

Many interrupt systems end up overloaded. One ends up writing a mini operating system to manage all the desired outcomes! And that can be a mess for sure.

In the P2 chip, a couple things were done to help with all that:

One is a priority and event system. Events trigger interrupts, and those break the program flow due to early implementation choices made that simplified the chip and made the power budget sane. There are three priority levels and 16 events that trigger on incoming signals as well as on chip events and other core on chip.

The other was polling modes so one can wait and employ whichever mode made the most sense.

Finally, interrupts happen after instructions complete. Doing this came with some controversy! But, it seriously simplified the chip and helped to draw the lines where the developer has choices to make and good options to make them.

Somewhat... I more often see the ability to run some fixed-function blocks (RTC, as you mentioned; also ADC running scheduled conversions with a digital comparator on conversion calling interrupt, as an example) running at this low a clock, with the model being that these low-speed peripherals wake up something else. Having the ability to run a useful set of peripherals /and/ do arbitrary very slow computations to decide about changing clock isn't universal. As an example, even if you had that capability, if you wanted to wake on a complicated condition of an ADC read, you might end up lower total energy use to wake up on the ADC conversion to the RC filter low-MHz speed, do the your computation, and either go back to sleep or continue to wake further, rather than do the computation itself at 32 kHz -- and certainly the former could be lower latency, depending on the complexity of computation.