It's a 4x4 configuration of the separately available Xilinx/AMD AIE-ML accelerator, available on Xilinx alveo platform IIRC.

VLIW vector units optimized for AI (-ML suffix) with runtime reconfigurable network on a chip letting you optimize "streaming" the data between individual cores.

The way "AMD IPU" device was implemented, which embeds the system in some new AMD CPUs, the previous drivers (which were Linux/RTOS only) didn't work.

I was actually in the middle of reverse engineering how it was exposed in Phoenix (7940hs) APUs to write custom driver for Linux based on the one shipped for windows.