> I guess it will have to be able to route around broken cores?

Yeah, but you'll also have to route around broken routes, and that starts to get a bit too much chicken-and-egg problem for me.

I guess you could design something akin to error correction codes, meaning you're resilient to X failures. Ex: a 64-bit bus could have physically Single Error Correction, Double Error Detection, which IIRC would be 72 physical wires.

That means any wire can completely fail, but you still have a 64-bit bus (indeed, the 8x error-correction wires could all fail and you'd still have a 64-bit bus).

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At some point, it makes more sense to cut the chips out, test them for reliability. Then cut the router out, and test those for reliability, and then finally glue them together.

On the other hand, doing it all on one wafer has cost savings / manufacturing simplicity. The math is likely difficult for optimizing over costs, production speeds, and so forth.