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Comment by throwbadubadu | Hacker News Reader

> The outcome is transistors capable of operating at terahertz frequencies, offering speeds 10 times as fast as that of the silicon-based transistors used in current chips.

Why? We are single digit gigahertz, so terahertzes should be ~ 100 times faster?

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The clock frequency is single-digit gigahertz. But digital signals have to propagate through multiple layers of logic gates, so the transistors have to switch much faster.

At a glance, the article doesn't make it clear whether the "terahertz" speed refers to switching frequency or gain bandwidth (fT). You can definitely get transistors with fT in the hundreds of gigahertz range right now.

> digital signals have to propagate through multiple layers of logic gates, so the transistors have to switch much faster

I don't think this is accurate. Are you saying that in digital computers each individual transistor switches faster than the clock rate of, say, 3 GHz? I think there is one clock signal that is distributed to all transistors and they turn on/off synchronously at this rate. The GHz number on the processor advertisement is the switching rate of all transistors, not some hypothetical 'system rate' which would somehow be much lower?? Please clarify or correct me if I am mistaken.

I think it's easier to see if you jump up 1 level of abstraction from transistors to logic gates.

Imagine an adder made up of logic gates. The gates aren't inherently synchronous - they don't have a clock input - signals appear at their inputs and some time later propagate to their outputs.

To make the adder synchronous you need flip flops at the inputs/outputs and a clock.

If you squint a bit you can view most designs as blobs of async logic sandwiched between sync elements (gated by the clock).

We can see that a signal might have to go through a lot of gates/transistors between flip-flops and so the gates (and their underlying transistors) will necessarily need to be able to switch faster than the clock.

This is the beauty of asynchronous logic: you don't need the flip flops and the clock - you need a yes-this-is-it signal propagating along the results.

You’re mixing up time and frequency. For a signal to propagate through multiple logic gates in one clock cycle, each gate must switch in a fraction of a cycle. That means a single gate could switch more often (higher frequency) if it were by itself. But it’s not.

(Technically, many gates do switch more than once per cycle since their inputs change at different times. But their outputs are only latched at the end of the cycle, so any extra switching is ignored.)

For digital computers, clock speeds are single digit GHz. For analog circuits, ~100 GHz is achievable in silicon. E.g., automotive radar chips, communication systems etc.

This THz comment relates to analog circuits, which is supposedly around a factor 10 higher with this new tech.

If you want to learn more, read about Fmax and Ft of transistors.

We're at single digit gigahertz for an entire chip, not a single transistor.

Not an EE, but my guess is that current transistors can likely operate at a much higher clock rate than current chips.

The problem is that when you pack them together, they get far too hot to permit dennard scaling to reach the limits of the individual transistor.

This one's not because of heat, but because signal had to go from the beginning of a stage, through several transistors, to the end of the stage

So the transistors switch fast individually, but the speed of the chip is limited by the slowest path in any stage, where you wait for every transistor on the path in series

Ah, right, thanks for correcting me.

Out of curiosity, how long are these paths generally?

Low single digit millimeters for current chip designs.

One reason that clock speeds are going above 5 GHz these days is that chips are getting smaller. That means shorter signal propagation distances.

So, when I talked about the length of the path in number of transistors, I oversimplified a bit. The length of the path would be measured in nanoseconds (or even picoseconds).

That number depends not just on the number of transistors, but also on the routing delay (are the interconnect wires between transistors long or short? How high is the resistance/capacitance?), and a lot of low-level details of the fabrication process that are extremely not public

But say you buy a brand new CPU and it's clocked at 5 GHz, you can easily get a rough estimate of how long the critical path is, since 1/5GHz = 0.2ns

What you can't easily get is the speed of the transistors or the number of transistors in the critical path, that info is not public, and you could only make a very rough guesstimate.

I recall reading some decades ago about dividing chips into separate domains that would commuicate asynchronously, precisely to shorten the longest path and increase the max frequency.

It's my understanding modern processors do indeed do this to varying degrees.

Yep, the term you might be thinking of is "clock domains". This is good if you want different parts of the chip to run at different frequencies, potentially saving a lot of power & gaining perf where needed

Single transistor level frequency is different than chip level frequency.

Each clock stage has many layers of transistors

PCIe 5.0 does 32 Gbit/s per lane, which means you need to run at least at 32GHz and probably more if you want to sample the signal more than once. So no, we are at way higher frequencies already.

I think that the current state of the art is 224 Gbit/s with PAM-4 modulation, which means 112 GHz :O

It is intended only for the highest end network gear, the range is very limited, and requires very special and expensive cables.

> Why? We are single digit gigahertz, so terahertzes should be ~ 100 times faster?

*1000 times

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