There was a comment on .. slashdot or similar, where someone explained that the massive L0 cache of the CRAY (8MB ?) meant it could sustain it's "limited" throughput, whereas an intel quad core would peak above then plummet due to spilling.
8MB was the main memory, but it was made from really high speed (and super expensive!) static RAM chips instead of the dynamic RAMs most other machines used. Other machines used SRAMs for caches, so I guess you could consider the Cray 1's main memory to be a cache.
The Cray had 8 "A" address registers but also 64 "B" registers. In the same way you had 8 "S" scalar registers plus 64 "T" registers. The main memory was highly interleaved so you could very quickly load and save blocks of B and T registers as well as the vector registers. You can think of B as a sort of cache for A and T as a sort of cache for S, but you had to explicitly handle this in your program.
Thanks for all your informations.