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They did, but to get it running as well as they did they had to deviate from generic ARM by adding support for the x86 memory model in hardware. Apple was in a position to do that since they design their own ARM cores anyway, but the off-the-shelf ARM reference designs that most other players are relying on don't have that capability.

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> They did, but to get it running as well as they did they had to deviate from generic ARM by adding support for the x86 memory model in hardware.

Note that this is actually very cheap in hardware. All ARM CPUs already support memory accesses that behave similarly to x86. It's just that they're special instructions meant for atomics. Most load and store instructions in Aarch64 don't have such variants, because it'd use a lot of instruction encoding space. The TSO bit in Apple's CPUs is really more of an encoding trick, to allow having a large number of "atomic" memory instructions without needing to actually add lots of new instructions.

You can do it with standard ARM instructions these days.

You could always do it with instructions itd just be slow no?.

I vouched for this comment, but it looks like you're shadow banned. You might want to email support.

> these days

Which instructions?

Those that are part of FEAT_LRCPC.

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