Besides, even if you could enable these DSP cores you'd be hard pressed to do anything useful with them, I don't believe there's any public documentation or tooling whatsoever for Cadence DSPs.
Going in and fixing that blown trace inside of an IC is beyond the capabilities of almost everyone because decapping a chip renders it inoperable.
edit: here's someone talking about running decapped chips. https://electronics.stackexchange.com/a/400899
Decapping with extreme prejudice.
Not if somebody's put a metal layer on top of it. You can only meaningfully fiddle with the top surface of a decapped chip.
The SMU reads the eFuses to determine what to lock down. So you can interrupt this process via JTAG and re-enable all the locked down cores. There is a window of a couple of milliseconds after de-asserting reset to halt the SMU.
I have no idea if this still works on newer chips with the AMD Secure Processor. There was some mention of a JTAG password in the leaked AMD documentation on the Web.
I'm not into that stuff anymore, I'm playing around with FPGAs now. No more locked down security processors to get in your way.
Most chip fuses are "antifuses": you pass high current through them, and instead of evaporating a fusewire like in normal fuses, it causes physical changes that reduce resistance.