https://www.youtube.com/watch?v=pzyZpauU3Ig
The engineering to handle that power density is insane. Technically its less power per mm^2, but the chip is the size of a dinner plate.
EDIT: The video was taken down, but looks like the web archive got it:
https://web.archive.org/web/20230812020202/https://www.youtu...
As well as Vimeo (thanks morcheeba): https://vimeo.com/853557623
My largest design as approximately 23 x 12 inches. Maintaining thermal efficiency and uniformity across the entire surface is where the real challenge lies. We had an extremely tight uniformity specification (0.1 deg C). This could only be achieved through a complex design process that entailed writing genetic algorithms to evolve and test solutions using FEA. In the end it was a combination of sophisticated impingement cooling and other techniques that did the job. That project was seriously challenging. I like projects that absolutely kick my butt. This one definitely did.
I can tell you that we worked very hard to try and see if we could accomplish the objectives using forced air (fans). That effort involved laser-welded fins with sophisticated airflow management, techniques to break-up the boundary layer (which impedes optimal heat transfer) and powerful centrifugal fans. It worked well, yet it was large and sounded like a jet engine.
Ultimately, while still complex, fluid-based thermal management offered a far more compact solution that could exist in a room with people not having to wear hearing protection. In addition to that, with a fluid-based system you can move the hot side to a different room.
I wonder, how do all the contacts in the 20,000A power distribution plate that is bolted on top of the wafer-scale die line up? The engineering involved in just making that part work must be crazy.
If we presume the wafer consumes a large percentage of that (say 20kW out of the 24kW max) and that they are feeding the "wafer" with DC at 1v, then they /do/ need to feed in 20,000 amps to deliver 20kW of power at 1v.
So yes, 20kamp is a lot of current, but it is within the "power budget" the device seems to express in its marketing material.
For comparison, one of the workstation AMD EPYC processors uses ~400W under peak load, and would use approximately ~320A peak current. It's only ~30x more current... modern CPUs use an enormous amount of current these days.
We have EPYC chips with ~100 cores at ~200w TDP. So each core is around 2W in the AMD chips. Core voltages are ~1v with modern CPUs. So that's 2A per core.
850k cores at 20kA is very much lower than the AMD chips. Must be massively parallel, lower-performing cores. But it's quite feasible that it needs 20kA.
The CS-2 system on their website specs out at 23kW peak. So all this lines up with each other.
As far as benchmarks and utility of such systems, I am not sure if they've proven it out.
I guess this is a process limitation? i.e, the stuff you would need to make an appropriate step down isn't compatible with the other stuff they need?
1. Process limitations (no high voltage devices, poor analog characteristics, limited resistor choice, etc)
2. The skill set for power device/analog IC design is very different than digital design (and harder to recruit for as the talent base is relatively small).
3. On chip power converters universally suffer from poor inductor quality which trashes your efficiency (thus increasing cooling demands as well).
From a business perspective it would be quite risky and likely not cost effective.
As for skillset, there are a bunch of IP companies with silicon proven designs available. I'm sure they didn't design their SERDES or PLL(s) in-house either.
They also have another design advantage here. I believe they're not IO limited with their bumps.So they can use most of it for power, which is much better than any DC-DC solution.
Cerebras has evidently scaled them up a bit (and repatented them, according to the video).
Interesting early application (if not the first) from the 1970s: http://www.hp9825.com/html/hybrid_microprocessor.html
Weirdly - CFD has been zeitgeisting me here on HN the last couple of days - I have been talking about FluidX3D - and have been attempting to compile it this AM locally on windows with failures (about to see if I can plop it into a docker)
Never thought youd be doing CFD calc to keep a stable temp flow over 1.6 trillion transistors to keep them evenly cooled - did ya?
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In watching that above CFD vid - I was led to start thinking if CFD could be applied to the ways AI models/GPTs communicate or calculate.
I wonder if one could use an CFD anaolgies to the data flows through AI models/systems such as OpenAI.
It would be interesting to look at the OpenAI GPT Store's entanglements through the lens of CFD and determine where relations might be made for how stacking GPTs might communicate through their Tapestry.
An CFD-heads care to dive in?
I wonder if one were to treat 'token flow' in a CFD manner in which one can visualize how tokens are assigned attention scores.
GPT claims to not be able to visualize the attention score matrix for the tokens - but assuming it could - it would seem as though it should be easy to visualize attention matrices in a CFD visual.
https://i.imgur.com/jzZ1wsP.png
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Or I sound like an idiot. Lets ask GPT. haha
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(also - in super expensive machines , why aren't sheets of AeroGels used as gaskets if you want thermal separation.
Imagine taking an AeroGel powder and mixing it with Silicone - and having a super thin, flexible material, such as D3 - which has a melting point of 134c/273f....
So - mixing aerogel with D3 as a gasket would be good, and with D3 being a non-newtonian it works well for shocks. A space gasket as it were.
There are reposts with that same link.
Maybe it revealed too much and was taken down?