Xilinx, for example, used to be very friendly about making really cheap or even free FPGAs available to academic users. This is because those users lead either directly to design wins (some academic designs go big, NSF style) or they become corporate users who are familiar with Xilinx gear.
But the software was crap, and they would have gotten more wins if the software wasn’t so awful.
"EDA software is crap" is so close to an axiom around here that I think Vivado doesn't get the credit it deserves. The synthesis flow has been rapidly modernizing and supports a chunk of VHDL-2019. The bundled simulator still lags on support and features, for reasons that are pretty easy to understand.
That’s too bad. I once got a small pile (8?) of max-spec Virtex-5 chips, for free, FedExed from Xilinx. Xilinx apparently valued them so little that they didn’t even bother putting the full address on the envelope. Tracking it down was fun.
The only remotely supportable way to synthesize images for them was to run a primitive CentOS 5 container on a big server — the Windows version of the tools were still 32-bit, and 4G of address space was too little for the synthesis workflow. Even with the magic 64-bit RHEL/CentOS-only build, it would take 45 minutes or so for the tools to notice any errors during synthesis.
Fun times.