Is it possible to use big and fat CPU registers instead of cache? There might be no wasted clock cycles and no delay.
Once you have enough registers, having more mean lowers active utilization for any given instruction (bad use of space, vs. fast pipelined access to cached stack) or higher levels of parallel instruction dispatch (much greater complexity, and even greater inefficiency for branching misses).
Then you have to update instruction sets, which could be impossible given how tightly they fit in current instruction sizes.
Ergo, increasing register banks is a major architecture & platform change from hardware to software redesign, with heavy end user impact, and a fair chance of decreasing performance.
In contrast, anything that improves caching performance is a big non-disruptive win.
Then think of registers as just part of the fetch & store pipelines for staging operations on stack values.
Forth goes all in with this approach.
If you add more registers, the cost per register increases rapidly, and you very quickly hit your limits.
If you make registers wider, that's still very expensive, and you introduce extra steps to get to your data most of the time.
So no, you can't do that in a reasonable way.