Anyone have insight on:
Why don’t they position the SOC to have the HBM in the center with the CCDs and XCDs on the perimeter?
Seems to me that would yield lower “wire length” through the interconnect for each CCD/XCD to all of the memory.
Why don’t they position the SOC to have the HBM in the center with the CCDs and XCDs on the perimeter?
Seems to me that would yield lower “wire length” through the interconnect for each CCD/XCD to all of the memory.
Also, the physical interconnect between the XCDs is different than the HBM.
The core systems of interconnect are at the base most center-most (well, there's a passive interposer too, but it's just wires): the IOD. These intermediate connections across the chips on top of them, the IOD next to them, and the memory.
The die-to-die links, on the other hand, have extremely short wire length limits (less than a centimeter iirc for UCIe). At the physical layer, you just waste a bunch of power and area driving a high voltage to make the signal go further. Do that enough and you basically wind up with a PCIe PHY.