Cortex A57, Nintendo Switch's CPU | Hacker News Reader

Cortex A57, Nintendo Switch's CPU

chipsandcheese.com

> The SoC also contains a cluster of four A53 cores for power efficient processing, but Nintendo has chosen not to use them.

The rumor I've heard is that there's a bug in the system crossbar which makes which core CCX you enable after reset the only choice you can make until the system is fully reset. That is, if you enable the A57 CCX, later enabling the A53 CCX triggers the bug and vis versa, even with the first CCX disabled when enabling the second.

If I recall correctly, the "Mariko" revision of the X1 completely removes or disables the A53 cores.

I can't wait until Nvidia finally releases a Tegra based lineup for consumer/prosumer devices.

These days I have a Jetson Agx Orin sitting on my desk. It's mostly for testing CUDA code which will be deployed in the field, but it's a surprisingly capable workstation. Where else do you get 64 GBs of unified memory attached to a somewhat capable GPU?

The Mac Studio, that's where. I believe Nvidia can and will pull of similar feats.

If they do, most likely Windows and ChromeOS will be the only ones being supported by OEMs.

They could be their own OEM. They're doing it for the Jetson, they're doing it for their shield devices.

Put a downsized version of the grace hopper chip in there, call it AI-DevBox and it will sell.

> Where else do you get 64 GBs of unified memory attached to a somewhat capable GPU?

AMD has many APUs with decent GPUs, you won't run CUDA on them but the graphics capabilities are there.

ROCm can run on some APUs, and then you have accelerated PyTorch enabling running Whisper and other fun models like that.

Not decent at all in the sense that ROCm never supported any of them.

Oh and sadly limited to 128-bit memory buses. Orin is at twice the mem bw in this regard, hopefully AMD will address that.

> It brings some unique features to the table too, like a flexible register file where multiple 32-bit entries can be used to hold 64-bit or 128-bit results.

Is this like the Z80 being able to use B and C (8 bit) as BC (16 bit)?

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