Comment by retrac | Hacker News Reader

Comment by retrac | Hacker News Reader

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As I'm sure most of us know, the x86 lineage goes back nearly 50 years. Many ideas that went nowhere, were taken as design decisions, and are forever etched in silicon.

One of my favourite examples is the x86 task switching support. The 386 had everything needed to implement context-switching and multitasking -- in hardware. (That notion was in vogue, once. See the ICL 2900.) If you set up the right structure in memory, and turn on the hardware task switching, x86 processors will automatically context switch all of the registers in and out of that in-memory structure, at the appropriate privilege boundaries (interrupt, return from interrupt, etc.) So your kernel can switch between processes like this (more or less):

    mov next_proc_ptr, tr
    iret

It also provides IO port protection - there's another table that lets you specify which ports the process can access, which the processor will examine, when an IO instruction is executed in user mode, presumably for something microkernelish.

Now that's the good ol' CISC spirit. It's quite a complex feature and yet I'm not sure any OS ever used it.

> It's quite a complex feature and yet I'm not sure any OS ever used it.

They did.

Linux used x86 hardware task switching and TR (task register) for years. See "struct tss_struct" and "switch_to" in older kernels.

Linux also allowed userspace processes to get hardware-managed access to individual I/O ports using the per-task x86 I/O port bitmap, and to local segments using the x86 LDT which were useful for running 16-bit code in a 32-bit task.

The hardware task switching was eventually changed to software task switching. By that time, software switching was faster, and it was always more versatile. This change removed the hardware-imposed limit on the number of processes and threads Linux could support.

Here's a nice article about the evolution of task switching in Linux. https://www.maizure.org/projects/evolution_x86_context_switc...

Even if no OS used it I bet it has been used - the era of the 386 saw a decent amount of bare-metal specialized uses of the hardware. Some would nominally run on DOS, some didn’t bother with it at all.

> I'm not sure any OS ever used it

When nobody uses such a feature is typically either because it has worse performance then alternatives or some missing feature. There have been many such cases in x86.

Interesting! Can you explain why OSes don't use it? I'd expect that it would be more efficient than doing the same thing with different instructions.

Originally, probably because it was inflexible. You have to use the in-memory layout required by the hardware, and you can't do anything not supported by the hardware. Later, it didn't get updated (probably because no one used it) so today it won't save things like the MMX and SSE registers, which makes it even less useful.

It's certainly much faster today to use sequences of mov instructions. In practice, it's a block move of multiple registers to memory/cache. That's something any modern pipelined and microcoded processor will have specialized support for. What instruction or instructions generates that internal action, is largely beside the point.

It didn't save the x87 FPU registers either, however a task switch set a flag in MSW / CR0 that caused a trap on the next instruction using these registers. The idea is that they are used infrequently, so it's better to only switch the FPU context when required.

This is no longer so true today, however the Linux kernel for example doesn't use any floating point or vector instructions, in order to avoid having to save these registers on every system call or interrupt.

The real inflexibility was scheduling (see my other comment)

> the Linux kernel for example doesn't use any floating point or vector instructions

it doesn't use them by default, but code that needs the FPU can call kernel_fpu_begin() to save those registers if needed. https://yarchive.net/comp/linux/kernel_fp.html One big user is the AMD graphics driver: https://lore.kernel.org/amd-gfx/ee26b06b-f1a0-5a8f-388c-13c1...

It would only be more efficient if user mode tasks jumped directly to each other without any kernel involvement. This is actually possible, but probably useless except maybe some very specialized embedded applications. If you already have a privilege level change and pushing of registers on the stack, a hardware tasks switch just does useless extra work.

One might think that since interrupts can switch tasks, you could set up a simple round-robin scheduler by hooking this mechanism up to the timer interrupt somehow, or have device drivers in separate tasks that become active when receiving an interrupt.

But a "task state segment" on x86 is actually more like a pre-allocated stack frame, with interrupts creating a linked list of these. A task can't be reentered while it is active, and it is supposed to exit by returning to the previous task that was interrupted. Anything else requires software scheduling.

The only reason to ever use this mechanism is for handling exceptions on a specially reserved stack (for example when the kernel stack overflows).

Sound like it's a hardware implementation of cooperative multitasking.

The way processors work, if the single instruction / automatic on interrupt etc method does the same things as do it yourself in your code version, about the only thing you're saving is instruction decode bandwidth and compiled code size. But that's usually not a large enough savings to matter.

And then you get the inflexibility: There's a limited number of hardware task slots; I think you can pick which registers to save (or rather how many to save), but you always save all of them: a kernel syscall might be more judicious and only save the registers it uses (of course saving all registers if returning to a different task); it's hard to change because software must run on old and new cpus; etc.

There's exceptions to the rule of thumb. Rep mov can be faster than doing it yourself. It's also quite possible for a combined operation to do two things at the same time rather than one after the other.

I believe iRMX, Intel's own OS for the 386, did use those features.

Linux did use the TSS in its early days on the i386. I think they changed it because performance wasn't very good.

i looked so long to implement hardware task switching only to find modern OSes decided it wasnt to be used. still not sure im onboard with that decicion haha. great example!! =)

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