It's the size of the caches, memory bandwidth, and high core count, of some of these mainframes that make them interesting to me. It could be fun to play around.

I'm sure they eat electricity like crazy though.

Mainframes have to implement a fifty years old architecture, and I suspect they have vastly smaller engineering teams, since their market is orders of magnitude smaller than those of Intel or ARM. Also I seem to remember IBM being seriously hostile towards independent benchmarks.

Also, if they were competitive wrt performance, people would be using them. In real life they are rarely found outside of financial institutions.

Almost 20 years (I'm getting old) ago, IBM had the eCLIPz[0] project to combine things from their Mainframe (Z) and POWER systems - it resulted in the POWER6 and z10. I assume that a lot of that sharing is still going on between the two series.

"The z10 processor was co-developed with and shares many design traits with the POWER6 processor, such as fabrication technology, logic design, execution unit, floating-point units, bus technology (GX bus) and pipeline design style, i.e., a high frequency, low latency, deep (14 stages in the z10), in-order pipeline.

However, the processors are quite dissimilar in other respects, such as cache hierarchy and coherency, SMP topology and protocol, and chip organization. The different ISAs result in very different cores – there are 894 unique z10 instructions, 75% of which are implemented entirely in hardware. The z/Architecture is a CISC architecture, backwards compatible to the IBM System/360 architecture from the 1960s. [1]

[0] https://speleotrove.com/decimal/IBM-z6-mainframe-microproces...

[1] https://en.wikipedia.org/wiki/IBM_z10