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Comment by kens | Hacker News Reader

Author here. This chip is pretty obscure, but I was looking at it for another project and figured I might as well write it up. Any questions?

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I just wanted to say thank you for all of these write-ups, and for the restoration and reverse engineering work that you do for the retrocomputing community.

Here's a question: how has this implementation changed in modern nano-scale ethernet implementations? Modern ethernet cards are asked to do much more offloading and processing, potentially including application protocols like TLS and DMA not just from memory but directly from NVMe devices as well. Given that we can now spam out transistors by the billions, are things like 10-bit counters still implemented via clever dynamic logic in hardware, or is there a more brute-force approach in use today?

I looked at the datasheet of a random modern Ethernet chip (ENC28J60) and it's simpler than I expected, doing much less than the old Intel chip, although it includes the low level "PHY" circuitry, which was a separate Intel chip in the olden days. I expect that the newer chip has things like 10-bit counters, but they would be implemented with standard cell logic (i.e. computer-generated layout of gates) rather than the hand-optimized circuitry of the Intel chip.

On the other hand, you can get a chip like the W5300 which includes the whole TCP/IP stack along with ARP and ICMP, presumably running on an internal microcontroller.

https://ww1.microchip.com/downloads/aemDocuments/documents/O...

https://www.wiznet.io/wp-content/uploads/wiznethome/Chip/W53...

High end NICs like Mellanox ConnectX are probably more similar to the 82586 in terms of breadth of functionality. They have (R)DMA, hardware timestamping, encryption, etc. Although, I wouldn’t expect to see much hand crafted logic design outside of the very high speed signal paths like in the serdes.

Minor detail whilst I read through this (I'm on a quest to understand my childhood Apple IIe, and at just the level to start understanding ripple counters): I think it's 10Mbit or 10Mb/sec ethernet, not 10MB/sec.

Thanks, I've fixed that.

Hi Ken, thanks for another excellent article! I just wanted to add that I recently bought an Intel EtherExpress 8/16 for my 486 PC and it uses this chip. So although the chip may be obscure, it still finds its way into the hands of new users even today. :)

The fact that I just got this card and had to search around the net for drivers and documentation, and now your die photos are available - I'm just amazed. What a cool chip and card.

> The idea of Carrier Sense is that the "carrier" signal on the network indicates that the network is idle.

Wouldn't a carrier indicate that the network is busy? Actually, Ethernet is a baseband system and so doesn't actually have a carrier, but for Alohanet you would only have the carrier when a transmitter was on even if it wasn't actually sending 1s or 0s at that instant.

That's nice simple logic that is laid out in a way that makes your reverse engineering straightforward. I really appreciate these articles because sometimes I build discrete logic circuits for fun so I see a lot of beauty in these things.

One part I didn't follow 2qs where then pseudorandom element is introduced. This seems like it can implement variable delays in powers of 2 based on the mask.

The first counter simply counts, so when you sample it you get a pseudorandom number. (Assuming the sampling time is random.) Then applying the mask gives you the power of 2 scaling.

Thanks, makes total sense. If the first counter is free running then it should look pretty random if sampled when there are collisions as those would be random themselves. Love how simple the solutions are when transistors were expensive.

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