That looks like a pure marketing slide to me. I don't think it would make sense to actually have separate dedicated silicon for these.
That being said, it's pretty common to have dedicated silicon for video codecs. It normally takes the form of a little DSP with custom instructions to accelerate operations specific to the codec.
I'm guessing this is a distinct region of the chip and not integrated with CPU/GPU since they scale up by replicating those blocks and wouldn't want to redundantly place that hardware. Having it separate also allows a team to work on it independently.
I think the relative size of the media engines is accurate in that slide, so then it comes down to how large the ProRes parts are in other chips. They are probably a couple of the unlabeled regions next to the performance cores in the M1 Pro die shot below, but I don't know which.
https://images.anandtech.com/doci/17019/M1PRO.jpg Taken from: https://www.anandtech.com/show/17024/apple-m1-max-performanc...
And video decoding/encoding is definitely at least GPU-adjacent, since it usually also involves scaling, color space transformations etc.
Maybe I'm misunderstanding what you're saying, but the slide is of an A17, not an M3 chip.
The A17 floorplan looks nothing like that either.
On a GPU, you didn't have an option to interleave normal program stream with specialized partial-decoding instruction. You put encoded frame in and you get decoded frame back, the media engine was separate block from compute.
Though this is also changing; see Intel GuC firmware, which has (optionally) some decoding, encoding and processing based on compute.