Qualcomm Snapdragon X Elite Performance Preview: A First Look at What's to Come
anandtech.com
anandtech.com
What Qualcomm has is a modem and modem patent monopoly. There were early Android SoC competitors e.g. nVidia Tegra. The issue was the modem. Not the CPU.
Now that 3G is being turned completely off in much of the world, the last vestiges of that advantage are going away and Qualcomm will have to learn to compete on a more level playing field.
Even low cost Mediatek SOCs have a built in standards compliant 5G implementation.
Too bad it doesn't run Windows. Sincerely, the purchasing department. /s
Upstreaming is clearly a higher priority now than it's been in the past, e.g. "Upstream Linux support now available for the the Qualcomm Snapdragon 8 Gen 3 Mobile Platform" [1]
Disclaimer: I'm a Qualcomm employee.
[1] https://www.linaro.org/blog/upstream-linux-support-now-avail...
If they actually sustain this effort I can see this new chip becoming a success regardless if it beats the M2 or not. It only has to have decent performance and decent linux support. Fingers crossed, I hope they succeed.
EDIT - looks like there's GPU support too. https://www.phoronix.com/news/Linux-6.5-MSM-Adreno-A690
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With the recent series of patches released by Linaro, the following features are enabled for the Snapdragon 8 Gen 3 Mobile Platform:
Qualcomm® Kryo™ CPUs, including DVFS (Dynamic voltage and frequency scaling) and Power Management
System foundation: Clocks, Power controllers, PMICs Low-Speed I/O: I2C, SPI, RTC, Buttons, LEDs
High-Density Storage: UFS 4.0, SDXC
High-Speed Peripherals: PCIe Gen3 and Gen4, USB Version 3.1 Gen 2, USB-C PD
Qualcomm® Hexagon™ Processor SubSystems: Audio, Sensors, Compute and Modem
Mobile Display Subsystem + DSI Engine, Touch Controller
Communication: WCN7850 Bluetooth
https://www.qualcomm.com/news/releases/2021/03/qualcomm-comp...
The risky thing is "violating license agreements." Licensing a RISC-V core from a company under specific terms, getting bought out, and then changing trajectory of your product with that IP in a way that might violate the terms could result in the company coming after you. Put more simply, "violating the terms of a license agreement means you could get sued." This isn't strange. It's a complete non-story.
The other real risk is one that exists in any processor design, that it costs tens of millions of dollars to develop validated, high-end, high-performance and energy efficient processors, no matter the ISA, and tooling them is an entirely different matter. These risks mean the vast majority of Production-Ready designs come from corporations that need to ship high volume, high margin products, based on projected returns. There's relatively little actually "open" about the processors from SiFive, Ventana, Rivos, etc, other than the fact they adhere to a specific version of a ratified software standard, a PDF you can download. If you come at it from a software point of view, all of the "ingredients" are basically proprietary. You aren't getting masks, RTL files, DV tools, bringup tools, or any capability to validate any of those are what you expect. You cannot reasonably modify and reproduce them -- a single wafer on a modern process can take months to actually pattern before the packaging process even begins. And they aren't going to give it to you, because that's their competitive advantage and the reason you buy their cores, instead of their competitors cores.
The whole bellowing about "proprietary ISAs" or "ARM vs RISC-V" on places like this is mostly totally misinformed upvote farming, and has no bearing on how reality actually works.
You can't really beat Intel and AMD unless you're at least as good as supporting the hardware and peripherals and for as long. I can see Intel and AMD getting better at power use but I have a hard time seeing ARM ecosystem become as open as the PC one.
Worth a read:
Amazon is the most successful manufacturer of Arm server chips, accounting for just over half of Arm-based server CPUs currently deployed, while some chipmakers are also now betting on Arm-based Windows PCs.
This information comes from a report issued by Bernstein Research which estimates that nearly 10 percent of servers across the world contain Arm processors, and 40 percent of those are located in China, as we reported earlier.
But that total is beaten by just one company – Amazon – which has slightly above 50 percent of all Arm server CPUs in the world deployed in its Amazon Web Services (AWS) datacenters, said the analyst.
For a desktop, if you don't care about power and heat, then this will have inferior performance.
Nuvia had a core designed for server chips when Qualcomm bought them, and Qualcomm publishing benchmarks at an 80 watt TDP, tells me that their chip isn't going to be well positioned to compete on power draw, heat and battery life against next year's chips, especially without any sort of efficiency core at all.
What's stopping Qualcomm from manufacturing their own phones and laptops and sell them directly to consumers?
* An unfused SoC, so no secure boot etc. The Efuse VPP pin is tied to ground so no possibility of bricking it by blowing the fuses inadvertently.
* Fully open bootloader, e.g. U-Boot based.
* Mostly complete register documentation for the SoC, that would be good enough.
* Mainline Linux support.
Such a board would take the open source world by storm.
Competitive very high performance cores already available for licensing include SiFive P870, Ventana Veyron as well as Tenstorrent Ascalon or Alastor.
We just need the SoC.
Refer to e.g. youtube to see it in action.
I have personally used qemu-user, another solution, to run ARM binaries.
> Regardless, the primary purpose of the Linux demo was to showcase that Linux was working on the Snapdragon Elite X as well – that it’s not just for Windows – as Qualcomm has aims of getting the SoC into Linux laptops as well.
Some person on the internet [1] says "The good news is that the exclusivity of Microsoft's Qualcomm 8cx series has ended. Moving forward, we will be able to encounter the 8cx series in a greater variety of form factors. For instance, there are plans to incorporate the 8cx Gen4 into Chromebooks as well." I'm not sure if exclusivity of 8cx Gen4 is different from X Elite though.
E.g. 128-bit memory wide bus in case of LPDDR type of memory is really just 8x 16-bit channels or, in a different word-size configuration, 4x 32-bit channels.
If that is so, my understanding is that Intel Tiger Lake with its 2x 64-bit channel design would equal to the same 128-bit memory bus width as M1, although, coupled with different type of memory chip technology - DDR4 instead of LPDDR.
For about two decades, mainstream consumer x86 platforms have almost always had a 128-bit memory bus. On desktop platforms with DDR4 and earlier, this can be accurately described as dual-channel, and that's the terminology marketing departments and end users are most familiar with. But it's never been accurate for mobile systems that use LPDDR, and DDR5 makes it less accurate for desktops, too.
High-end platforms like AMD's Threadripper have supported memory configurations like 256-bit ("quad channel DDR4") and 512-bit ("8 channel DDR4") and now 768-bit on the latest EPYC servers, and over the years Intel has had server or workstation platforms with 192-bit (LGA 1366 socket), 256-bit (LGA 2011), 384-bit (LGA 3467), 512-bit (LGA 4677) memory interfaces (per socket). I believe Apple was the first to ship something wider than 128-bit in a laptop, and AMD plans to be the second in a year or so (not too surprising given what they've been shipping for the console market).
Yes, that is now more obvious to me after your clarification and a short history walk-through. Thanks!
Given that Apple never discloses much about their design, I was never actually 100% sure if the difference would only be related to the number of memory channels and thus capability of a memory controller or there was something else that was novel and that nobody else did. I am much more familiar with the server grade CPUs and was aware, as you very neatly summarized, of the differences and high memory bandwidths available in that spectrum. I was checking just this morning how many channels there are on Epycs and last generation of Xeons!
Since we have different 128-bit wide designs available, it is interesting that Apple M1 chose to have 128B cache line size instead what others have - 64B. I never thought about that but it makes me wonder if it is more challenging to design a memory subsystem with the cache line size larger than what your DIMM actually supports.
According to the page 78 from https://www.micron.com/-/media/client/global/documents/produ..., burst read operation will take 16 clock cycles to clock in, and roughly 4 more cycles to get the data out.
At 2133Mhz clock cycle is 468 ps or 0.46 ns so to get 64 bytes out it will take 20 cycles x 0.46 ns = 9.2 ns. This means that to populate the 128B cache line it will take at least two such bursts leading to a total latency of 18.4 ns. This latency translates to ~6GB/s of burst reads. I guess this is a number only for a single channel and it's relatively close to what Micron mentions in the PDF: "Up to 8.5 GB/s per die".
What I don't understand is how the LPDDR4 data rate transfer of 3200 MT/s (~25GB/s) is achieved then? The biggest package Micron LPDDR4 module comes in is 2 channels, hence, per their numbers we get a maximum bandwidth of 2 x 8.5GB/s = 17GB/s.
Okay, this is wrong, I couldn't find it before but there is a larger Micron LPDDR4 module equipped with 4 channels and thus this theoretical LPDDR4 limit can be hit. E.g. MT53D1024M32D4 from https://www.micron.com/-/media/client/global/documents/produ...
Windows came up a few times in RISC-V's foundation own talks.
An official announcement would follow hardware availability. rather than the other way around.