Show HN: Use an EEPROM as Programmable Logic | Hacker News Reader

Show HN: Use an EEPROM as Programmable Logic

github.com

22 pointsdusted15 comments

Reminds me of TheRasteri's video on using an EEPROM to convert CGA TTL video signals to EGA/VGA : https://www.youtube.com/watch?v=vwKA1z8tg1g&t=261s

This was routinely done for 2 decades or so. Small (e.g. 32x8, 256x8) fast bipolar proms were extremely common for things like address decoders in the 70s and 80s. I've used fast Cypress cmos proms (cy7c244) more recently. Cypress also made registered proms which probably make some applications easier. Using lisp to specify it is clever, tho...we usually had to make due with pen and paper.

Another interesting strategy is to use RAM as programmable logic. It's faster, which can be beneficial in some situations, and is obviously easy to change on the fly. The catch is that you'll need a mechanism to bootstrap it - which can be as simple as copying the contents of an EPROM using a counter on startup/reset.

Interesting idea! With DRAM it becomes slightly funky because you want to allow for refresh, but with SRAM it's certainly a cool idea to get more speed, if you can live with the sizes (about the same as EEPROMS) and price.

Could this be used to build a super minimalistic Ben Eater style CPU?

It can function as a NAND gate, and anything can be built out of NAND gates. At that point it might be simpler to just use actual NAND gates though :)

Definitely, if you just need some nand gates, this is probably the worst way of doing it, where it can be of some use is when you want to describe more complex behavior, where you quickly end up with a mix of tens, hundreds or thousands of gates.

It is not fast but very interesting:

https://www.youtube.com/@DrMattRegan/

Cool channel, much of it over my head, thanks.

Yes, however, it's best suited for the complex parts (logic that needs a lot of inputs and few outputs) due to the fact that the eeproms it generates data for are arranged as 8 bit output.

It might also be somewhat slow compared to discrete gates, the AT27C512 I'm using is rated at 45ns access time, while a normal DIP gate is usually around 5.

That said, 45 ns, means it should function up to about 20 mhz if I'm not totally wrong (which I've been known to be before).

I made this because I need some logic for my DEC J-11 CPU and to keep it period-ish-correct didn't want to bring in an fpga, I'll use it for power-up settings and controlling memory bus access. I could have used a PLA or GAL, but I don't have any and I have about a kilogram of the beautiful old quartz window EEPROMs :)

> and I have about a kilogram of the beautiful old quartz window EEPROMs :)

You mean UV erasable EPROMs (window = for letting the UV in).

EEPROMs are erased electrically and thus don't have a window.

it generates data for are arranged as 8 bit output

There were/are x4 proms (e.g. am27s10 == 256x4).

45 ns, means it should function up to about 20 mhz

Theoretically. If you're careful.

I need some logic for my DEC J-11 CPU

Cool...I keep wanting to do something with my J-11s beyond play with ODT. What are you doing for storage? That seems to be the problem with most PDP-11 projects...most of the available OSes are deeply tied to storage related DECisms.

I'm going from scratch with the J-11, it won't run UNIX, my only real "goal" is to have a self-contained unit, something with a bit-mapped display and direct keyboard input, not just a serial port. I will probably use sram, and for permanent storage, long term, I'd like to do more with EEPROMs, but for starters, probably an SD card.

Yes. See [0], and especially the very last link [1] in that comment (it's a very nice write-up on exactly how to do that).

[0] https://news.ycombinator.com/item?id=37548907

[1] https://bailleux.net/pub/ob-project-gray1.pdf

So cool, thanks.

Reply on news.ycombinator.com