Newbie questions, what is a 'softcore'?
Also, how many transistors does this equate to? Because IIRC PowerPC is quite an extensive instruction set, and some instructions are quite involved
Also, how many transistors does this equate to? Because IIRC PowerPC is quite an extensive instruction set, and some instructions are quite involved
Using the tools specific for each FPGA vendor, e.g. AMD (i.e. Xilinx), Altera (to be spun off soon by Intel), Lattice or Microchip, the HDL code can be synthesized into logic gates, then placed and routed, then the bit string with the corresponding configuration can be loaded into an FPGA.
If in the same FPGA one also implements a memory controller and peripheral interfaces, it can be used instead of a standard CPU.
The disadvantage is a low clock frequency, typically of a few hundred MHz, and high power consumption in comparison with a standard CPU with the same performance.
The advantage is that you can be certain that the CPU does only what you want, with no hidden functions or backdoors, and that you can customize it in ways that are not possible with standard CPUs, e.g. by adding instructions or accelerator blocks for performing some tasks that are done inefficiently in software or for interfacing with certain hardware devices that have real-time requirements that are difficult to achieve in a non-deterministic standard CPU.
Microwatt fits in a Lattice ECP5 FPGA with 85,000 LUTs (plus some block ram). Not sure how you'd get to transistors from that, wild guess times by 15 maybe? (But then the FPGA also has other special hardware blocks intended for interfacing with DDR RAM and other things, so those would be more as well).
You can see how the Power instruction decode is implemented https://github.com/antonblanchard/microwatt/blob/master/deco...
It's also an unwise search term on the web. Ask me how I know!
The big thing that complicates figuring out a transistor count for a soft CPU core is that FPGAs have hardware multipliers, which would be pretty big if you had to build them yourself.
Of course, this is all very approximate.
There goes "tiny"...
There are big FPGAs that cost many thousands of $.
Medium-size FPGAs, which may cost a few hundreds of $, have a few hundred thousand LUTs.
An evaluation board for the medium-to-small ECP5 FPGA is $100.
It comfortably surpasses the capacity of most of the Actel aerospace FPGAs that I tend to work with.
And I think it's so "micro" that the majority of all of Lattice's FPGAs wouldn't fit it either.
And the Lattice ECP5 is advertised with 85k LUTs, which would seemingly limit its use to edification as instantiating this softcore would consume the entire chip. For any other purpose if you wanted a chip that was only a CPU, you would buy a CPU.
Any PowerPC core, even a relatively small one like this, is much more powerful than the soft cores that are used in FPGAs when minimum size is desired.
There are also a few other bigger open-source POWER cores, which can be used for higher performance.
Technically it's a core that's supplied as RTL (code). There's nothing stopping you using it in custom silicon instead of on an FPGA. Whereas a "hard IP" core is already compiled down to a specific technology and can only be used there. It's possible for a hard macro to be for an FPGA, but it would be for a specific product line. A "hard macro" for custom silicon would be specific to a particular fab process.