TSMC: Ecosystem for 2nm Chip Development Is Nearing Completion | Hacker News Reader

TSMC: Ecosystem for 2nm Chip Development Is Nearing Completion

anandtech.com

111 pointsmfiguiere19 comments

Have the 3nm process used in Apple's A17 Pro chip delivered on the promises? The initial tests seemed to indicate that there's barely any efficiency over the previous node.

Are the new nodes for real on the performance and efficiency? The "nm" doesn't mean much since a while but at least we were getting considerable improvements from node to node, is that still the case?

Yes it has. Apple fixed the recent watt and temperature issue. In addition A17 Pro delivers significantly more transistors. Lastly, N3E will be an improvement over N3B that Apple used.

N3E will be an improvement in cost, but cutting down on the number of EUV layers vs. N3B will have a negative impact on transistor density.

Seems like N3B is a bit of a flop: simply too expensive for anyone but Apple.

It will have lower density but higher performance, lower power, cheaper, and better yield. With all these things combined, you can easily just design a bigger chip with more or same amount of transistors.

Almost everyone is moving to N3 from N4 (not N5), the performance jump is not as impressive as the numbers which are based on N5->N3.

Its hard to get a good impression without more data points but the improvements we're seeing in the A17 on N3B are not very impressive relative to chips like the A16 made on N4P. It's really difficult to see the full picture but most signs seem to point to N3B being a marginal improvement for a significant increase in cost. For nearly anyone but Apple that is difficult to justify which is why Apple is the only big customer for N3B right now. We'll see how things change once TSMC gets N3E in mass production but it might not make things much better. N3E will probably feature lower average transistor density than N3B thanks to SRAM regressions so its difficult to tell if its performance will be meaningfully better than N3B in real world cases. It will be cheaper though, which is the important part.

> It will be cheaper though, which is the important part.

Indeed. For a long time, new nodes could be read as: more ICs/wafer = lower cost/IC = lower cost/transistor in those ICs. Or bigger ICs with more transistors.

Leaving it up to designers to choose between cheaper/smaller/lower power, or use extra transistors to achieve higher performance at similar cost/IC.

Maybe that lower cost/transistor 'law' doesn't hold anymore for these latest nodes? Or not as much as it used to?

Not saying Moore's law is dead! But it talks transistors/IC. Not so much about the cost of those transistors.

So maybe we're seeing some decoupling here between Moore's law & cost/transistor gains for newer nodes? If so, that would certainly affect market segmentation between products built on older vs. built on newer nodes. As opposed to the 'newer = better everything' we're used to.

Note this is just speculation on my part.

Moving to a new process node gives you a choice of increasing performance or lowering power draw.

Apple has been unusual in that they have not pursued "performance no matter what it does to power draw and heat" like other companies have in recent years.

> On the CPU side of things, Apple’s initial vague presentation of the new A15 improvements could either have resulted in disappointment, or simply a more hidden shift towards power efficiency rather than pure performance. In our extensive testing, we’re elated to see that it was actually mostly an efficiency focus this year, with the new performance cores showcasing adequate performance improvements, while at the same time reducing power consumption, as well as significantly improving energy efficiency.

https://www.anandtech.com/show/16983/the-apple-a15-soc-perfo...

Others may make different choices.

The early reporting said the A17 improved the performance on the big cores by 10%, but not the little cores. If they had used the node change oooortunity for performance increases, you would expect to see the gains on both the big and little cores.

> Apple says the performance cores are 10 percent faster than they were before, a relatively mild improvement, while the efficiency cores are more efficient rather than being faster.

https://arstechnica.com/gadgets/2023/09/apples-new-iphone-15...

How small the features need to be until electromigration destroys the devices in a matter of days/weeks/months?

Although I guess "3 nm" is nowhere near that small in reality.

Sounds like the next round of iPhones may be even lighter if they can keep using these improvements to reduce battery sizes

It's going to be very exciting if we get it down to picometer, even if it is the equivalent to 0.9nm.

Did IBM beat them by over 2 years?

https://arstechnica.com/gadgets/2021/05/ibm-creates-the-worl...

I'm guessing not, since right at the top of that article, the average density of IBM's 2nm process is compared directly to that of TSMC's 3nm.

If you compare densities however, IBMs 2nm process claims 333MT, and the actual (not "estimated" as per article from 2021) density of TSMC 3nm is 215MT.

That number 333MT means millions of transistors per square millimeter, I get from that linked ars tecnica article. That seems like a much better way to compare different technologies in chip fabrication, because of the well known fact that these gate widths have lots of nuances that impact how many gates per unit of space can be used.

Why don't we just use "millions of transistors per mm^2"? The concept seems obviously useful, until now I never thought of it.

Seems like a Goodhart's law situation to me. It would not stretch my credulity very much to see MT/mm^2 rapidly become just as nuanced (as feature size) if it were used for primary marketing.

One problem is that the measurement depends on what you're using the transistors for. You can fit more logic tranistors per mm^2 than cache transistors on recent nodes (capacitance is really annoying).

There is likely a giant difference between demonstrating a process vs scaling it to high yields at volume production.

IBM is great at flashy demos that don't pan out in the end.

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