From what I know of each, they're fairly close together, but a few small things like the clever encoding of logical immediates (e.g. and x1, x1, 0x3fff70000000 is a single instruction; you don't need to waste a register to load the immediate) in AArch64 make it seem friendlier to me.
That's not to say RISC-V isn't a good ISA. The whole point of RISC is to be a good target for compilation, not humans.
I did not mean zero preprocessor, I meant a conservative/frugal usage a simple pre-processor to avoid to spawn another insanely complex SDK dependency of the code which will be a pain to create a real life alternative. Basically, RISC-V is meant for multi-instructions per line assemblers (semi-colon...).
But you can do both with RISC-V, there's nothing to stop you.
m68k used to be my favorite, until RISC-V happened.
Not them, but I would say it's backwards compatibility guaranteed for RV64GC, which happens to be very nice and clean, free of the baggage other ISAs have.
The licence fee is only valid in some countries though.