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Self-Hosting (Almost) All the Way Down [video]

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122 pointspabs317 comments

Imagine a world where FPGAs had better performance then CPU/GPU. And we all had one as our main processor. Lots of possibilities! You could possibly "install" a program in the true sense of the word, like installing a kitchen cabinet. It could have totally isolated resources. Containers would really be contained. Neural network architectures themselves could learn (not just the weights).

> Imagine a world where FPGAs had better performance then CPU/GPU.

Is that even theoretically possible, assuming we don't do the obvious thing and make normal CPUs slower to force it to be true?

Also:

> You could possibly "install" a program in the true sense of the word, like installing a kitchen cabinet. It could have totally isolated resources. Containers would really be contained.

This is just hypervisors with guests, and has absolutely nothing to do with FPGAs.

> Is that even theoretically possible, assuming we don't do the obvious thing and make normal CPUs slower to force it to be true?

No. With all the space they waste being reconfigurable, the max frequency they can support at the logic element level is much lower just due to how much distance the signal has to travel without attenuating too much.

Less about physical space, more about propagation delays. The configurability of an FPGA doesn't come out of nowhere; it's a bunch of multiplexers and pass transistors which route signals around and control how they're processed by CLBs, and those elements all add delay, limiting Fmax.

> This is just hypervisors with guests, and has absolutely nothing to do with FPGAs.

It really is not. On an FPGA, additional logic does not slow down the other logic. In a hypervisor it does!

> On an FPGA, additional logic does not slow down the other logic.

It absolutely does. As the amount of logic in a design increases, it becomes increasingly difficult (and, eventually, impossible) for a place-and-route algorithm to generate a layout which meets timing constraints.

Oops. I was thinking of specifically the case where each "container" was already confined to its own space on the chip, so placing/routing would happen individually. But in the general case it does make sense that more logic in the middle of some code will affect everything that has to be placed around it.

Maybe my understanding of FPGAs is wrong, but isn't that an issue at design-time and not an issue at run-time?

Well if you declare that anything your router can't place can not exist then yes.

But in reality - no. There's a reason why people didn't already drop everything in favor of FPGAs and it's because they don't scale (and also are horrible at thermals).

Also, cost. And tools.

Congratulations, you invented modular [POTS] PBX and network switches.

I like to imagine a world where this is not only possible, but common. Not many people need to do this, but there's incredible power in being able to identify a specific date and time in cvs or git history and recreate literally everything, precisely and reproducibly, from that date and time.

Phenomenal work and a really engaging talk!

Cue Lenovo buying Framework within 2 years.

You commented on the wrong article. The "Lenovo exec promises 80% of its devices will be consumer-repairable by 2025" is here.[1]

[1]https://news.ycombinator.com/item?id=37816670

Dang it

Isn't this the same depth as normal? Just instead of a bitstream for an FPGA that defines how it functions there is microcode for the CPU which defines how it functions.

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