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Comment by kllrnohj | Hacker News Reader

> Intel will go the Apple way though

Hmm, curious what the "Apple way" is here..

> simpler cores

Apple's cores are very far from simple. They are much larger than the other ARM CPUs on the market, and this is also why they are faster than other ARM CPUs on the market.

> trading die area for ever larger caches

Apple has big L1 comparatively, but L2 & L3 are nothing special. Certainly nowhere close to the massive caches that AMD's X3D offers.

> also on-die memory

Apple doesn't have on-die memory. AMD is the only company to have shipped on-die memory to consumers (they were also the first to ship it), and they only did so on GPUs so far. Nvidia & Intel are playing with it for datacenter products, though, but that's about it (H100 & Xeon Max respectively)

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I think simpler cpu meant to simplify x86, like the x86-s proposal [0]

0: https://www.intel.com/content/www/us/en/developer/articles/t...

> Apple doesn't have on-die memory. AMD is the only company to have shipped on-die memory to consumers

What distinction are you drawing such that Fury X interposers count as “on-die memory” but apple’s literal stacking of the LPDDR on the actual die doesn’t?

Apples technique is more advanced than fury actually: fury is just on-package, not on-die, but apple is literally doing v-cache style stacking of the whole memory subsystem right on top of the die.

Of course fury x was earlier, but die stacking is a more advanced technology, there is a reason AMD didn’t do that for 5+ years after fury x. And apple actually beat AMD to market with on-die stacking, by several years (epyc v-cache was 2022 or 2021) with a more advanced implementation (the whole memory subsystem rather than just v-cache).

That's not how it works at all. Apple has nothing similar to V-cache.

> That's not how it works at all.

What isn’t how what works? Use your words.

(People literally are in such a race to pick a fight and defend their best friend AMD they forgot to make the rest of the post lol. Simply say the most mild thing and AMD people trip over themselves to do this stuff constantly, it’s funny.)

Do you think OP is referring to something other than fury x/Vega when they said “gpu shipped to consumers”? That’s the only thing that comes to mind, literally there are only less than a half dozen consumer gpus from AMD in the stacking era so I don’t know what else it would be.

If you mean true memory in the die, not stacked, not just a cache - AMD has never shipped that to consumers (or professionals) in a gpu. Nobody puts memory in the gpu because it would be a waste of die space.

But like, gotta defend AMD, better hammer that downboat and drop a pithy six-word/single-sentence reply. Social media is constantly seething with the AMD defense force looking for fights, gets super old.

Like, it was literally less than 30 seconds from clicking post on my comment to seeing your debate determinating cliche. What fine discourse we have here.

> Apple has nothing similar to V-cache.

Thanks for the second sentence.

AMD’s consumer gpus don’t use v-cache. Apple is using the same memory-on-package technique that fury x and Vega use. Rdna3 cache is not v-cache, just another flavor of mcm.

No, HBM on silicon interposer is not the same as LPDDR on an organic package. One's an order of magnitude faster than the other.

AFAIK Apple only uses a silicon interposer to connect the CPUs. The memory is on standard interconnects through the package like AMD's chiplet approach or the ancient Intel Clarksdale.

> but apple’s literal stacking of the LPDDR on the actual die doesn’t?

There's pictures of Apple's silicon all over the Internet, didn't think to bother even looking at one?

https://cdn.mos.cms.futurecdn.net/EWuFBHNeGSfhjJfoWFxL7D-102...

It's very obviously not on die. On package maybe, but definitely not on-die.

Since you're talking about die stacking i assume you're now talking about their "low end" phone parts. That's a quite different technology from V-cache, foveros, or even Apple's "UltraFusion." It's also not at all a unique technology to Apple, it's very common in the phone SoC space where power consumption is so limited that the thermal issues are mostly negated.

The Xeon Max memory is in the package but not on the same die. The package contains 4 CPU dice and 4 stacks of HBM dice.

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