Comment by em500 | Hacker News Reader

Comment by em500 | Hacker News Reader

If you're wondering about the actual performance of these cores, I think they'll end up around 300-350 single thread Geekbench6 points (comparable to Intel Goldmont N4020, or the ancient Core 2 E8400/Q9500). This is based on extrapolating ARMs public estimates (35% better than A55, or up to 90% of A73 performance).

The A55 (2017) wasn't great from a perf/watt standpoint (modest power savings but massive performance reduction vs their A7x middle cores), and it doesn't look like the A510 (2021) is a big leap forward. It's nowhere near Apple's very impressive efficiency cores (which reach A7x like performance at lower power than the A55). Anandtech has more details:

https://www.anandtech.com/show/16693/arm-announces-mobile-ar...

    As of the latest generation of SoCs, Apple’s efficiency cores were around 4x faster than any Cortex-A55 based SoC. Which, running at roughly the same system active power, also made them 3-4x more efficient in the traditional benchmarks. As presented, a theoretical A510 SoC won't be able to close that efficiency gap at all.

See also https://www.anandtech.com/show/16983/the-apple-a15-soc-perfo... especially the last graph, which shows how far ahead Apple is on perf/watt.

Doing a proper fair comparison of microarchitectures is incredibly difficult. Even measuring the the power consumption of the core alone may be rather tricky. Especially if you don't have access to the design details.

So when it says 'same system active power' I'm assuming it means measuring the power consumption of the SoC with the Apple core vs the power consumption of the SoC with the A510s in when they're both running software that should stress the little cores and not use the big cores.

It could be that the Apple core microarchitecture is genuinely better on perf/watt, it could be the different process nodes the cores were built on. It could be the choices made by the implementation engineers when they were making the chip (you can get huge swings in power consumption, area and timing results just by changing some settings). Apple for instance could have really valued perf/watt and spent lots of time on the implementation side here, where a Qualcomm/Samsung SoC they just slapped it in, cranked up the frequency as hard as they could to get nice headline numbers and sticking in a tight area budget and called it a day (which Arm has no control over). Perhaps some other vital system component (e.g. the DDR controller) has bad power efficiency and a lot of the power is being lost to that.

To do an actual comparison you'd need to run a power simulation of the two core RTLs side by side, look at workloads that actually represent what you want to do with the efficiency cores and try to make the systems they're running in as close as possible. Only Apple, being the only company with access to both sets of RTL, could do this and if they have I seriously doubt they're telling anyone about the results.

If you compare numbers between A510 on TSMC N4 and A16 on N4 (as close as you'll be getting without detailed info about layout libraries), you'll find Apple's little core winning in both performance per watt and overall performance.

I think the real tradeoff was area as Apple's little cores seem to be a lot bigger than A510.

There's perf/watt but also area on the core that's an important factor. Watt and area are often related but not always. Do you know how the A510 cores and Apple's efficiency cores compare on area?

Apple’s efficiency cores are significantly larger than A5x cores.

Too bad not everyone can afford the die space ;) All the economics etc are different for Apple since they don't sell the chips by themselves, and basically buy all the fab capacity for a new TSMC process.

Exactly, and this is one of the main reasons why Apple is unmatched in performance in the smartphone space: they can afford much larger transistor budget than other companies since they're vertically integrated.

This isn't always true.

Qualcomm Snapdragon 8 Gen 2 has 16B transistors on TSMC N4.

Apple A16 has 16B transistors on TSMC N4.

One of the biggest disappointments of the new A17 was getting a major node jump and only increasing the transistor count by 3B.

Qualcomm’s SoC includes a modem. Apple’s modems aren’t integrated.

Qualcomm x24 was 33mm2 on TSMC N7. The max transistor density of that process is 100M/mm2 giving an upper threshold of 3.3B transistors, but analog circuits scale notoriously bad and I wouldn’t be at all surprised if the actual transistor count were 10-20x less than that theoretical upper limit.

Given the memory latency impact on in-order cores, I wonder how much of the gap is core design and how much is Apple's tending to fit much larger caches to their designs.

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