PCB High-Speed Delay Matching (a.k.a.: Why DDR RAM traces are so squiggly) [video]

Computer users may not realize the amount of effort that goes into a "simple" PCB design such as connecting CPUs with DDR RAM.

This youtube video is a practical advanced PCB tutorial that introduces the concept of Delay Matching. The electricity traveling along a pcb trace travels at a finite speed (based on board manufacturing details). DDR RAM is all parallel: meaning the CPU puts the bits on multiple wires and sends the bits down all the wires to communicate with RAM.

"Delay Matching" exists because these bits need to _arrive_ at the RAM at the same time. So, after laying out all the PCBs, the "faster" lines will get lengthened to "slow down" the fast bits, and make sure all the bits arrive at the same time.

Crazy things happen at 500MHz (2 nanoseconds per clock tick) or 1GHz or faster. As such, the faster-and-faster RAM gets, the closer-and-closer these "bit matches" have to be for anything to work at all.

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There's a few other issues like controlled impedance and such. But the delay matching lines are really obvious and immediately visible to the naked eye if you've ever inspected a motherboard.

This is also a reason why modern interfaces are favoring "parallel serial" lines, rather than a "parallel interface". Ex: PCIe x16 is 16 parallel lines, but each line is "serial" (that is, the timing doesn't need to match any other lines. Its 1-bit lines run 16 times, each single-bit line at its own speed). This makes life easier in practice for PCB layout.