What is RISC-V, and why we're unlocking its potential

But for me, the worst part is the non-choice. In the PC world, you can choose 10000 different PCs.

Again, I really admire the M1/M2, and the quality of apple products. But I returned an M1 on my previous job because of what I said above, and went to a ThinkPad X1 Carbon.

ARM suing them was simply because they are using a contract tailored for Server market and using it in Smartphone.

It looks like Apple's biggest lead is the TSMC node advantage and their ARM license. And they're not the only ones with access to TSMC fabs and ARM specifications...

As the parent alluded to, if there is a problem in the Android ecosystem you will almost certainly find either Qualcomm or Google in the middle of it.

ISA is the least important part in CPU. The hard part is having all drivers for the peripherals given chip has and knowing most of the chinese vendors it's straight to landfill after few years unless something becomes so popular community RE it.

In the early days of all of mainframes, minicomputers, and microprocessors companies slapped some hardware design together and then made un an instruction set for it. When the same company made a better, faster, shinier computer a few years later the hardware was completely different and the instruction set was completely different and everyone had to rewrite their software.

One of the best-known examples is the Intel 4004, 8008, 8080, 8086 and so on. None of them can run software for either later or earlier chips. Intel was reasonably good at making it not too hard to rewrite old software, but it still had to be done.

An Instruction Set ARCHITECTURE is an instruction set that is designed from the outset to be independent of any particular hardware implementation of it, and it is intended to make and sell machines over a long period of time that can all run the same software.

Not only that, but with, for example, the IBM System/360 introduced in 1964 they announced six different machines (Models 30, 40, 50, 60, 62, and 70) on the same day, with about a 20:1 "commercial" performance ratio (90:1 for "scientific" use) and a similar range of monthly rental costs (IBM didn't sell them outright).

RISC-V is similarly deliberately an Instruction Set Architecture, that works well with a very wide range of implementation techniques and cost/size, all of which can run exactly the same software (at least if it sticks to RV32I / RV64I).

The trial was set to begin on the 23rd. Not sure what the date is now. But you can see depositions being taken in August [1].

[1] https://www.courtlistener.com/docket/64938776/arm-ltd-v-qual...

The point being that they wanted the rights Nuvia had but without the obligations that Nuvia license implies - most specifically on fees.

And yes they have an architecture license but no the lawsuit is still open.

Copyrights cover documentation, and may cover the names of instructions. But creating something that's interoperable with x86, and doesn't violate those copyrights, should be considered fair use. In the same line of copyrighted APIs vs. competing implementations of said APIs. Basically: make cpu that eats binary code of >20y old x86 cpu, use new names for instructions, and write your own documentation.

But of course recent, high performance x86 cpus are still covered by many patents.

So what's legal are competing implementations of x86 cpus released ~20y ago, not using performance enhancing technology covered by still-valid patents. To do what? No market for those.

Not to mention Intel & AMD have legal teams that could make the going tough for anyone trying to do so. Even if legally allowed.

A big advantage for RISC-V is being a clean slate ISA, meaning its design takes into account many issues that were bolted on ad-hoc in other ISAs (32/64 bit, extensions, virtualization, compact instructions, etc).

And being a modular design, you don't pay the power/area cost if you just need a simple core.

Whether it's a universal good for the consumer or not is unclear. We could end up with significant fragmentation. But the compelling aspect of RISC-V is that companies can spin up their own cores to do all sorts of things without a lot of hassle with licensing. Either by writing one's own core or using an existing off the shelf one, and then tacking on whatever extensions or customizations that make sense for them

And thinking here far beyond what most people think of when they think of in regards to processors (phones, computers) but the fact that ARM cores are in practically everything these days from the MCU to the MPU level. Everything from light bulbs and ceiling fans to COVID tests to garage door openers to christmas lights or toys to drive and memory controllers to laptops and phones.

Think of all that diversity, and now consider what advantages a manufacturer can get by being able to roll up whatever they want, but still be able to use a common standard compiler suite, verification tools, skill set, etc.

RISC-V is the future, or at least a future. No doubt ARM and x86 will exist alongside basically forever, but RISC-V I think has crossed the point where it was a "maybe will be something" to a "it's happening" moment.

A really good introduction to RISC-V is designed, and why it is the way it is, by the original authors.

It left me with a very positive view of RISC-V, as well as reasonable knowledge of the ISA and ABI, which has since proven useful while writing/debugging assembly on the architecture.