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Comment by AceJohnny2 | Hacker News Reader

This presentation is more evidence that Moore's Law is dead. Nvidia and AMD can blame their partners, but the reality is that they're hitting increasingly costly technological hurdles.

Of course Nvidia can't just throw it's hands up and say "welp, we've hit the wall" when it has someone to blame.

It's fascinating to watch those predictions about the end of Moore's Law come true.

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Intel seems pretty confident that they will be able to get to 11nm in the next 5 years or so. Past that, pure shrinkage of transistors via purely "conventional" methods will mostly hit a wall, but everyone saw that coming.

There's been a lot of work on nanoelectronics. For example, some scientists recently announced at a semiconductor conference that they had found a way to bypass the diffraction limit completely, making 2nm features with a 650nm laser. Similarly, I know an engineer who worked on a massively-parallel electron-beam-based etching device, which could also be applied similarly at very small node sizes. There's a billion other technical challenges, but there's been a lot of progress in making features on the molecular level.

If anything, this is better than expected: EUV has had some serious problems over the past few years, yet its delay hasn't stopped the next few nodes.

Moore's law doesn't require that shrinkage continuing, though, as there are other technologies available. Memristors in particular may allow scaling faster than Moore's law would otherwise predict.

And then there is the third dimension to consider:

http://spectrum.ieee.org/semiconductors/devices/3d-chips-gro...

That comes with a very large set of engineering challenges but if those are overcome you can expect another big jump.

You still have the problem of dumping the additional heat. So AFAICT, 3D will only provide some incremental advancement.

Plus, even if cooling between layers were figured out, we'll probably just end up with lots of transistors that we can't all power on at once, since we're already at practical power draw limits for most devices.

We don't just need to cram more transistors on a chip, we need those transistors to use proportionally less power (preferably even less than that).

There are many ways to dramatically lower power usage if you're willing to accept slower speeds. Intel has recently demoed some extremely low-voltage transistors that used power in the microwatts. You can make up for this dramatically lower speed by adding far more circuitry using 3D chip-stacking.

Another possible solution is to use 3D chip stacking to add dedicated hardware for a wide variety of tasks, most of which is turned off when not being used.

There's the intermediate step to 3D - 2.5D. it's when you lay all you dies side by side, on another chip, instead of a pcb. It makes relatively easy to manage heat and you can get much more bandwidth at much lower power(much shorter wire distances). And it's already in use for high end fpga's.

You mean the multi-chip module (MCM) ? https://en.wikipedia.org/wiki/Multi-Chip_Module Those have been around forever.

Or something different?

He's talking about this:

http://www.eetimes.com/electronics-blogs/other/4210170/Xilin...

Cool! Thanks.

I wonder if the price will ever come down to the point where it's used in consumer devices.

The last time I did some reading into the limits of Moore's Law, about four years ago, the industry consensus was that ~12nm would be the practical limit for traditional CMOS scaling. It's interesting to see evidence that prediction does appear to be holding out.

12nm might be a technical limit - but if those 12nm transistors cost more than a 28nm transistor then nobody wants them.

The main reason for going small is cost - Silicon costs you per sq in - smaller transistors are supposed to buy you more hardware for the same money. If that stops there is less reason to go small.

To clarify, there are still advantages to 12nm, in that the speed of light allows the 12nm transistor chip to be faster (all other things being equal) than the 28nm chip. However, there are limited uses for that speed at this point, which bring into focus cost/performance.

Further, part of bringing costs down involves efficiencies of scale. If you don't have the scale, the price will limit the output. It might be back to the supercomputer world for those who need that particular extra bit of speed.

Well, we're staring at the end of shrinking silicon feature sizes all right. There might be more order of magnitude improvements in store with the use of new technologies, but we should certainly be prepared for a lengthy interregnum.

Moore's law will hold true another 20 years at least. New computing architectures will be the driving force, not silicon processes.

Moore's law only describes silicon processes:

http://en.wikipedia.org/wiki/Moores_law

It has nothing to do with computing architectures.

If you are going to be pedantic about it, you're wrong as well: Moore's law describes neither chipmaking processes nor silicon. It describes a quantity of transistors that are in an integrated circuit. In fact, the first integrated circuit was the Darlington transistor, which would have been germanium at the time, and also had nothing to even do with computing.

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