RV-Cure: A RISC-V Capability Architecture for Full Memory Safety

arxiv.org

16 points·hasheddan··7 comments

Cool that even RISC-V ecosystem is looking into this kind of issues.

Cool that almost all security research is now done using RISC-V, including this paper where the most experienced guy appears to be the one working at Arm (he was at gatech, like the others, before but has been at Arm research for six years).

Using RISC-V ISA, BOOM open source OoO core, and Berkeley's "FireSim" FPGA simulation environment.

I doubt that being the case, security research of production systems isn't done on RISC-V, and we still care pretty much about those other systems being used in large scale deployments.

Just recently we had quite a few reports from those efforts.

How are you going to go in and alter the ISA of that production (x86?) system to determine the best/cheapest way to increase security in future systems?

You can look for vulnerabilities in those production system, sure, and try to find work-arounds, but that's kind of short term tactics not fundamental research.

Intel, AMD, ARM, Qualcom, Apple, Samsung, NVidia,IBM, Oracle, Microsoft.... also happen to employ security researchers.

That is how stuff like SPARC ADI, MTE, PAC, Azure Sphere, CHERI, Morello, comes into existence.

You missed that the lead author on this paper is an Arm security researcher who decided to use RISC-V not Arm for this research?

For which I don't criticise him at all -- it's a very sensible decision.

How is it different from CHERI?

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