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He doesn't mention yield, which I hear is currently pretty bad on 3nm. And "just route around the bad silicon" might be easier said than done; widespread defects might create too many roadblocks to efficiently move data around your wafer-chip.

If that's not factored into his 3450 wafer estimate, it could be double that.

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This was my first thought reading this article. I am not an expert and my knowledge is limited.

When he mentions the prices of the wafers, does it come with the bad yields or without?

A knowledgable friend recently told me the wafer price is, you get what you get. This was in reference to a recent Apple story that TSMC was giving Apple a discount for bad dies, or something like that, on the 3nm node. I have no references.

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