A close look at the 8086 processor's bus hold circuitry | Hacker News Reader

A close look at the 8086 processor's bus hold circuitry

righto.com

61 pointsTomte14 comments

> Much of the complexity is probably due to the wildly different behavior of the pins between minimum and maximum mode.

That truly does seem to be a silly design (as does the pin count constraint that "excuses" it). "Gakulicious engineering by intel" could probably fill a decent textbook.

What else might've used this? 8087 doesn't seem like enough of a thing to justify an entire separated bus like this, were they thinking multiprocessor uses? were there any? "asymmetric multiprocessing" i guess it'd have to have been.

Yes, Intel had pointless restraints on pin counts; the 8008 processor was barely allowed 18 pins. So the 8080 designers were lucky that they got all the way to 40 pins. Federico Faggin has ranted about this in a few places.

As far as applications of the bus, multiprocessing was a big motivation. Intel had big plans with their Multibus. Intel had more plans for coprocessors as well. They introduced the 8089 I/O coprocessor to provide mainframe-style channel I/O, but it wasn't very popular.

More pins means more soldering when planting the chip on a mainboard (even if sockets are used, they need to be soldered, too) which increases time, cost and chances that something goes wrong and the entire mainboard must be discarded.

Yeah, but that's a balance like everything else. It's far too easy to end up somewhere where the complete design requires added complexity to figure out the state of the multipurposed pins (and that associated logic's additional pin count) that you end up with a harder to manufacture product.

Edit: adding that this is in the late 70s/early 80s where final integrators were using a bunch of 7000s-esque logic to glue the board together. Nowadays of course we can assume so many transistors on both sides of a trace that super generic sets of SERDES-style pairs makes sense nowadays for most complex buses.

Through-hole components would be wave soldered not done by hand - so no, time and reliability have nothing to do with it.

Just about any manufacturer would be reworking boards that failed QA not throwing them away.

had to go refresh my memory on the 8089; here's a manual in case anyone else is curious. Its fun.

http://bitsavers.org/pdf/intel/ISIS_II/9800938-01_8089_Assem...

Is the 8089 Intel's equivalent to Motorola's 6820 PIA? (I've never seen a 8089 in the wild - 6820s are often used in pinball machines)

No, the Motorola 6820 simply provides two I/O ports. The Intel 8089 is a complete processor with its own instruction set, acting as an intelligent DMA controller. So you can run complex programs on the 8089 to process the I/O data. The model is kind of like the I/O channels in an IBM mainframe; you're offloading I/O tasks from the main processor to a special I/O processor.

>were they thinking multiprocessor uses? were there any? "asymmetric multiprocessing" i guess it'd have to have been.

https://en.wikipedia.org/wiki/Intel_8089

As for pin count, google around a bit and find out how much trouble the relaxed attitude to pin count caused for Motorola. The 68K paid dearly for its many pins.

> you can have too many pins! i'm not going to say what that means but if you 'google around' for articles about the state of motorola fourty years ago you may find a hint

I'm getting flashbacks of segmented memory.

imagine the intersection of memory protection and address aliasing. We could've had layers and layers of more or less useless complexity and years of hardware designed so as to be impossible to secure, at its most fundamental levels.

Well, this certainly answers my questions on a previous righto submission about the implementation of minimum versus maximum mode. Thanks!

Thanks, Ken!

Reply on news.ycombinator.com