It goes beyond being inefficient. It's the wrong mental model.

Chip designers intuitively visualize interconnected blocks of logic. They draw rectangles with wires between them.

To learn this intuition, writing spaghetti Verilog code that runs in a simulator is counter-productive. It's a common mistake that people coming from a software background make all the time, and that has been discussed to death. So with some appeal to authority, trust us and learn proper hardware design, hopefully it will be more rewarding and will "click" faster.